1. Introduction to Micro Controllers & Embedded System Design Instruction set
Department of Electrical & Computer Engineering Missouri University of Science & Technology
A.R. Hurson

2. Instruction set of 8051 can be partitioned into five groups:
Arithmetic
Logical
Data Transfer
Boolean variable, and
Program branching
A.R. Hurson

3. Arithmetic instructions are:
Instruction Format
Length (byte)
# of machine cycles
Mnemonic
Operand
Semantics
ADD
A, Source
Add source to A
1-2 1
ADDC
Add with carry
SUBB
Subtract from A
INC A
Source
DEC
DPTR 2
MUL AB 4
DIV
A.R. Hurson

4. Arithmetic instructions
Since 8051 supports different addressing modes ADD A, for example can be written in different ways:
Instruction Format
Length (byte)
# of machine cycles
Mnemonic
Operand
Semantics
ADD
A, 7FH
Direct addressing 2 1
ADDC
Indirect addressing
A, R7
Register addressing
A, #35H
Immediate addressing
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5. Arithmetic instructions
Example:
ADD A, #34H ; Add 34 to the accumulator
MOV A, #25H
MOV R2, #34H
ADD A, R2
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6. Example: Accumulator contains 63H, R3 contains 23H, and PSW contains 00H:
A) what is the hexadecimal content of accumulator and PSW after execution of the following instruction?
ADD A, R3
B) What is the content of accumulator in decimal
ACC = 86H and PSW = 05H
Decimal content of ACC = ?
A.R. Hurson

7. Note: Add instruction could change the AC, CY, or P bits of the flag register:
Show the flag register contents after performing the following:
MOV A, #0F5H
ADD A, #0BH
F5H
+ 0BH
100H
CY =1 since there is a carry out
P = 0 since result has even number of 1s
AC = 1 since there is a carry from D3 to D4
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8. Add the following 5 bytes of data, the sum is kept in R7 and
Accumulator:
Address Content
40 7D
41 EB
42 C5 B
44 30
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9. MOV R0, #40H ; indirect addressing MOV R2, #5 ; setting loop counter
CLR A
MOV R7, A
AGAIN: ADD
JNC NEXT
INC R7
NEXT: INC R0
DJNZ R2, AGAIN
1s t iteration A = 7D, CY = 0  R7 = 0
2nd iteration A = 68, CY = 1  R7 = 1
3rd iteration A = 2D, CY = 1  R7 = 2
4th iteration A = 88, CY = 0  R7 = 2
5st iteration A = B8, CY = 0  R7 = 2
A.R. Hurson

10. Analyze the following: Adding 2 16-bit numbers and saving the
result in R6 (low byte of sum) and R7 (high byte of sum).
CLR C
MOV A, #0E7H
ADD A, #8DH
MOV R6, A
MOV A, #36H
ADDC A, #3BH
MOV R7, A
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11. Example: Write a sequence of instructions to subtract content of R6 from R7 and leave the result in R7.
MOV A, R7
CLR C
SUBB A, R6
MOV R7, A
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12. The general format of subtract instruction is: SUBB A - source - CY
In 8051, subtraction is performed as 2’s complement addition:
Take 2’s complement of subtrahend
Add it to accumulator
Invert carry
After the operation:
if CY = 0 the result is positive,
if CY = 1 the result is negative and destination has 2’s complement of the result.
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13. Analyze the following CLR C MOV A, #4CH SUBB A, #6EH JNC NEXT CPL A
INC A
NEXT: MOV R1, A
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14. Analyze the following CLR C MOV A, #62H SUBB A, #96H MOV R7, A
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15. Binary Coded Decimal
In an unpacked BCD, a byte is going to represent a decimal digit: high order half byte (a nible) is all zeros. i.e., 9 =
In a packed BCD, a byte represents two decimal digits
In adding packed BCD numbers, we need to make sure to check that each nible of the sum is not greater than 9. If it is then we need to add 6 (0110) to correct the result.
A.R. Hurson

16. Binary Coded Decimal
DA A instruction is intended to resolve the aforementioned issue (it adds 0110 to the low and/or high nibles as needed).
Note: DA instruction must be used after addition of BCD operands. It will not work after any other arithmetic instruction such as INC.
A.R. Hurson

17. Assume the following 5 BCD data is stored in RAM. Analyze the
Following code:
Address Content
40 71
44 37
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18. MOV R0, #40H ; indirect addressing MOV R2, #5 ; setting loop counter
CLR A
MOV R7, A
AGAIN: ADD
DA A
JNC NEXT
INC R7
NEXT: INC R0
DJNZ R2, AGAIN
A.R. Hurson

19. The general format of Multiplication operation is:
MUL AB ; A * B, places the result in B and A
MOV A, #25H
MOV B, #65H
MUL AB
25H * 65H = E99H
B = 0EH
A = 99H
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20. The general format of division operation is:
DIV AB ; Divides A by B, places the quotient in ; A and the remainder in B
MOV A, #95
MOV B, #10
DIV AB
B = 05
A = 09
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21. Logical instructions include:
Instruction Format
Length
(byte)
#of machine
cycles
Mnemonic
Operand
Semantics
ANL
A, Source
Logical AND
1-3
1-2
ORL
Logical OR
XRL
Logical XOR
CLR A
Clear A 1
CPL
Complement A RL
Rotate A left RR
Rotate A right
RLC
Rotate A left through C
RRC
Rotate A right through C
SWAP
Swap nibbles
A.R. Hurson

22. Logical instructions
As in case of arithmetic instructions, since supports different addressing modes each logical operation has different flavor, for example:
Instruction Format
Length
(byte)
#of machine cycles
Mnemonic
Operand
Semantics
ANL
A, 55H
Direct addressing 2 1
Indirect addressing
A, R6
Register addressing
A, #33H
Immediate addressing
A.R. Hurson

23. Logical instructions
Rotating the bits of accumulator to right or left has the following general formats:
RR A and RL A
LSB
MSB
Rotate Right
LSB
MSB
Rotate Left
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24. Logical instructions
Rotating the bits of accumulator to right or left through the carry has the following general formats:
RRC A and RLC A
LSB
MSB
RRC A C Y
MSB
LSB
RLC A C Y
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25. Logical instructions
Note: Logical operations can be performed on any byte of the internal memory space
XRL P1, #0FFH
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26. Logical instructions
SWAP A instruction exchanges the high and low nibbles within the accumulator.
D7 – D4
D3 – D0
Before
D7 – D4
D3 – D0
After
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27. Serializing a byte of data
This can be done by repeating the following sequence of instructions:
RRC A ; Move a bit to CY
MOV P1.3, C ; output a bit of data
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28. Write a program to transfer 41H serially via pin P2
Write a program to transfer 41H serially via pin P2.1, puts two high at the beginning and end of the data:
MOV A, #41H
SETB P2.1 ; High
MOV R5, #8 ; Loop counter
HERE: RRC A
MOV P2.1, C
DJNZ R5, HERE
SETB P2.1
A.R. Hurson

29. Write a program to count number of 1s in a given byte:
MOV R1, #0 ; R1 is the counter
MOV R7, #8 ; Loop counter
MOV A, #97H ; Desired value
AGAIN: RLC A
JNC NEXT
INC R1
NEXT: DJNZ R7, AGAIN
A.R. Hurson

30. Data Transfer instructions are:
Instruction Format
Length
(byte)
#of machine
cycles
Mnemonic
Operand
Semantics
MOV
A, Source
Move source to destination
1-2 1
MOVC
A+DPTR
Move from code memory
A+PC
MOVX
Move from data memory 2
DPTR
@Ri, A
PUSH
Direct
POP
XCH
Exchange bytes
XCHD
Exchange low order digits
A.R. Hurson

31. Data Transfer instructions
Internal RAM
Instructions that move data within the internal memory spaces execute in either one or two machine cycles.
MOV Destination, Source
allows data to be transferred directly between any two internal RAM and SFR locations.
Note: the upper 128 bytes of RAM are accessed only by indirect addressing and SFRs are accessed only by direct addressing.
Note: Stack resides in on-chip RAM and grows upward in memory.
A.R. Hurson

32. Data Transfer instructions
Example:
Note: Value (i.e., immediate addressing) can be moved directly to any A, B or R1-R7 registers.
MOV R1, #12 ; Load 12 decimal (immediate addressing)
; to register R1
MOV R5, #0F9H ; Load F9 (hexadecimanl) to R5
; 0 is added to indicate F as a number not ; a letter
A.R. Hurson

33. Data Transfer instructions
Example:
MOV A, #5 ; 5 will be extended by zeros to the left ; and loaded into a register.
; This will result A =
MOV A, #256 ; Moving a value larger than 8 bits will
; cause an error
MOV A, 17H ;17H is the address (direct addressing)
; of a location. Content of this location
; is moved to accumulator.
A.R. Hurson

34. Example MOV A, #55H ; Load value 55 in hexadecimal ; into accumulator
MOV R0, A ; Copy content of accumulator
; to register R0
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35. Data Transfer instructions
External RAM
The data transfer instructions that move data between internal memory and external memory use indirect addressing.
The indirect address is specified using a 1-byte address where Ri is either R0 or R1 of the active bank) or a 2-byte address
All data transfer instructions that operate on external memory execute in two machine cycles and uses accumulator as either source or destination.
A.R. Hurson

36. Data Transfer instructions
Look up Tables
Two data transfer instructions are dedicated for reading look up tables in program memory:
MOVC (move constant) uses either the program counter or DPTR as the base register and the accumulator as the offset.
MOVC + DPTR
Accommodates a table of 256 entries (numbered 0 to 255). The number of desired entry is loaded into the accumulator and the data pointer is initialized to the beginning of the table.
MOVC + PC
works the same way, except PC is used as the base register.
A.R. Hurson

37. Data Transfer instructions
Look up Tables
The table is usually accessed through a subroutine:
MOV A, #Entry
CALL Look-up 
LOOK-UP: INC A
MOVC + PC
RET
TABLE: DB data, data, data, …
A.R. Hurson

38. Boolean instructions:
8051 supports a complete bit-slice Boolean processing. The internal RAM contains 128 addressable bits and SFR space supports up to 128 other addressable bits. In addition, all port lines are bit addressable and each can be treated as a separate single-bit port.
Instructions that access these bit are: move, set, clear, complement, OR, and AND.
A.R. Hurson

39. Boolean instructions:
Instruction Format
Mnemonic
Operand
Semantics
CLR C
Clear bit
bit
SETB
Set bit
CPL
Complement bit
ANL
C, bit
AND bit with C
C, /bit
AND NOT bit with C
ORL
OR bit with C
OR NOT bit with C
A.R. Hurson

40. Boolean instructions:
Instruction Format
Mnemonic
Operand
Semantics
MOV
C, bit
Move bit to bit
Bit, C JC
rel
Jump if C set
JNC
Jump if C NOT set JB
Bit, rel
Jump if bit set
JNB
Jump if bit NOT set
JBC
Jump if bit set and then clear
A.R. Hurson

41. Boolean instructions:
Example: The following sequence of instructions performs XOR operation:
MOV C, BIT1
JNB BIT2, SKIP
CPL C
SKIP: (continue) 
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42. Boolean instructions:
Example: Suppose one wants to compute the logical AND of the input signals on bit0 and bit1 of port1 and output the result to bit2 of port1:
LOOP: MOV C, P1.0 1 cycle
ANL C, P1.1 2 cycles
MOV P1.2, C 2 cycles
SJMP LOOP 2 cycles
A.R. Hurson

43. Program branching instructions:
Branching instructions are intended to control flow of the operations in a program. They include call and return from subroutine, and conditional and unconditional branching.
Note that these set of instructions are enhanced by different addressing modes.
A.R. Hurson

44. Program branching instructions:
There are three variations of jump instruction: SJMP, LJMP, and AJMP which stand for relative, long, and absolute addressing, respectively.
A.R. Hurson

45. Program branching instructions:
The SJMP instruction specifies the destination as a relative offset. Since the instruction is two bytes long, the jump distance is limited to -128 to +127 bytes relative to the address following the SJMP.
A.R. Hurson

46. Program branching instructions:
The LJMP instruction specifies the destination as a 16- bit constant. Since the instruction is three bytes long, the destination address can be anywhere in the 64K program space.
A.R. Hurson

47. Program branching instructions:
The AJMP instruction specifies the destination as an 11-bit constant. The op.code contains 3 bits of 11 address bits.
When this instruction is executed, the 11-bit address replaces the low order 11 bits of the PC and the high order five bits of PC remains unchanged. The destination, therefore, must be within the same 2K block as the instruction following the AJMP.
A.R. Hurson

48. Program branching instructions:
Instruction Format
Mnemonic
Operand
Semantics
Format
Length (byte)
machine cycles
ACALL
Address 11
Call subroutine
aaa10001aaa 2
LCALL
Address 16
aaaaaa 3
RET
Return from subroutine 1
RETI
Return from interrupt
AJMP
aaa00001aaa
LJMP
aaaaaa
SJMP
Relative
eee
JMP
@A + DPTR
A.R. Hurson

49. Program branching instructions:
Instruction Format
Format
Length
Cycles
Mnemonic
Operand JZ
Relative
eee 2
JNZ
eee
CJNE
A, direct, relative
aaaeee 3
A, #data, relative
dddeee
Rn, #data, relative
10111rrrdddeee
@Ri, #data, relative
idddeee
DJNZ
Rn, relative
11011rrreee
Direct, relative
aaaeee
NOP 1
A.R. Hurson

50. Program branching instructions:
Instruction Format
Mnemonic
Operand
Semantics JZ
Relative
Jump if A = 0
JNZ
Jump if A NOT = 0
CJNE
A, direct, relative
Compare and jump if not equal
A, #data, relative
Rn, #data, relative
@Ri, #data, relative
DJNZ
Rn, relative
Decrement and jump if NOT zero
Direct, relative
NOP
No operation
A.R. Hurson

51. Program branching instructions
Jump Tables
The JMP @A + DPTR instruction supports CASE- Dependent jumps for jump tables.
The destination address is computed at execution time as the sum of 16-bit DPTR register and accumulator.
A.R. Hurson

52. Program branching instructions
Jump Tables
Example
Note: DPTR acts as the base and accumulator acts as an index.
Note: RL A instruction multiplies accumulator by 2 since each entry in the “jump-table” is two bytes long.
MOV DPTR, #JUMP_TABLE
MOV A, #INDEX_NUMBER
RL A
JMP @A + DPTR
A.R. Hurson

53. Program branching instructions
Jump Tables
JUMP_TABLE: AJMP CASE0
AJMP CASE1
AJMP CASE2
AJMP CASE3
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54. Program branching instructions
Example: Assume the jump table in the previous example starts at memory location 8100H with the following values:
Address
Content
8100 01
8101 B8
8102
8103 43
8104 41
8105 76
8106 E1
8107 F0
A.R. Hurson

55. Program branching instructions
a) What is the beginning and ending addresses of the 2K block of the code memory in which these instructions reside?
b) At what addresses do CASE0 through CASE3 begin?
8000H to 87FFH
CASE0 begins at address 80B8H
CASE1 begins at address 8043H
CASE2 begins at address 8276H
CASE3 begins at address 87F0H
A.R. Hurson

56. Program branching instructions
Subroutines and Interrupts
There are two variations of CALL: ACALL and LCALL using absolute and long addressing, respectively. Either instruction pushes the value of the program counter into the stack and loads the program counter with the address specified in the instruction.
The PC is pushed into the stack, low-byte first and high-byte second.
The bytes are popped from the stack in reverse order; high- byte first and low-byte second.
A.R. Hurson

57. Program branching instructions
Subroutines and Interrupts
Example: An LCALL instruction is at address 1000H-1002H and the stack pointer contains 20H, then the LCALL
Pushes the return address 1003H into the stack, placing 03H in 21H and 10H in 22H
Leaves the stack pointer containing 22H, and
Jumps to the subroutine by loading the PC with the address contained in bytes 2 and 3 of the instruction.
A.R. Hurson

58. Program branching instructions
Subroutines and Interrupts
Example: The following instruction
LCALL COSINE
Is at address 0204H through 0206H and the subroutine COSINE is at address 043AH. Assume stack pointer contains 3AH. What internal RAM locations are altered and what are their new values after execution of LCALL instruction?
Address Contents
3BH 07H
3CH 02H
81H (stack pointer) 3CH
A.R. Hurson

59. Program branching instructions
Subroutines and Interrupts
Subroutines should end with a RET instruction. This instruction pops the stack into the program counter to allow the execution of the instruction after CALL.
RETI instruction is used to return from an interrupt service routine (ISR). RETI also signals the interrupt control system that the interrupt in progress is done.
If there is no other pending interrupt at the time RETI is executed, the RETI is functioning the same as RET instruction.
A.R. Hurson

60. Program branching instructions
Conditional jumps
8051 offers a variety of conditional jump instructions, all specify the destination addressing using relative addressing, hence it is limited to a jump distance of -128 to +127 bytes from the instruction following the conditional jump instruction.
Note: The DJNZ and CJNE instructions are for loop control. For example, to execute a loop N times, load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop.
A.R. Hurson

61. CJNE instruction has the following general format:
Note: This instruction effects the value of CY flag to indicate if the destination operand is larger or smaller.
CJNE Destination, Source, relative address
Accumulator or one
of the Rn registers
Register, memory, or
an immediate value
A.R. Hurson

62. Program branching instructions
Conditional jumps
Example: The following code shows a loop that is iterated 10 times.
MOV R7, #10
LOOP: (begin loop) 
(end loop)
DNJZ R7, LOOP
A.R. Hurson

63. Program branching instructions
Conditional jumps
Example: Suppose a character is read from the serial port and it is desired to jump to an instruction designated as “TERMINATE”, if it is 03H. The following code shows this process.
CJNE A, #03H, SKIP
SJMP TERMINATE
SKIP: (continue)
A.R. Hurson

64. Write a program to get a byte of hex data from input port P1 in the range of 00-FFH and convert it to decimal.
MOV A, #0FFH
MOV P1, A
MOV A, P1 ; read data from P1
MOV B, #10 ; B is 0AH = 10 decimal
DIV AB
MOV R7, B
MOV B, #10
DIV AB
MOV R6, B
MOV R5, A
A.R. Hurson

65. Assume bit P2. 3 is an input and represent the condition of a door
Assume bit P2.3 is an input and represent the condition of a door. If it goes high, it indicates that the door is open. Monitor the door constantly, whenever, it goes high send a low-to-high pulse to port P1.5 to turn a buzzer.
8051
P2.3
P1.5
Buzzer
HERE: JNB P2.3, HERE
CLR P1.5
ACALL DELAY
SETB P1.5
SJML HERE
A.R. Hurson