1. ELEC 7770 Advanced VLSI Design Spring 2014 Technology Mapping
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

2. Synthesis: A Two-Step Process
Minimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit.
Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms:
Programmable logic array (PLA)
Standard cell library
Field programmable gate array (FPGA)
Other . . .
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

3. ELEC 7770: Advanced VLSI Design (Agrawal)
Standard-Cell Design
Obtain two-level minimized form.
Map the design onto predesigned building blocks called standard cells (technology mapping).
Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology:
90 nanometer CMOS
65 nanometer CMOS
45 nanometer CMOS
. . .
Optimize for area, delay, power, testability.
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

4. A Technology Mapping Algorithm
Use a small set of logic elements as building blocks, sufficient to construct any logic circuit.
For example, NAND. Building blocks may be two-input NAND gate and inverter.
MSOP is converted into NAND-NAND circuit.
Split all NAND gates of the circuit into two-input NANDs and inverters.
Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching).
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

5. ELEC 7770: Advanced VLSI Design (Agrawal)
A Typical Cell Library
Name
Area units (cost)
Inputs
Output function, Z
Inverter 2 A
NAND2 3
A, B
NAND3 4
A, B, C
NAND4 5
A, B, C, D
AOI21
OAI21
AOI22
XOR
S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill
1994, Section 7.7, pp
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

6. ELEC 7770: Advanced VLSI Design (Agrawal)
NAND3 Cell
Directed Acyclic
Graph (DAG)
(tree)
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

7. ELEC 7770: Advanced VLSI Design (Agrawal)
NAND4 Cell
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

8. ELEC 7770: Advanced VLSI Design (Agrawal)
AOI21 Cell
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

9. ELEC 7770: Advanced VLSI Design (Agrawal)
OAI21 Cell
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

10. ELEC 7770: Advanced VLSI Design (Agrawal)
AOI22 Cell
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

11. Technology Mapping Procedure
Obtain minimum sum of products (MSOP).
Convert to two-level AND-OR circuit.
Transform to two-level NAND-NAND circuit.
Transform to two-input NAND and inverter tree network.
Perform an optimal pattern matching to obtain a minimum cost tree covering.
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

12. Example: A Two-Output Function
Need four products: P1, P2, P3, P4 F1 A F2 A 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 4 12 8 1 5 13 9 3 7 15 11 2 6 14 10 D D C C B B
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

13. Two-Level AND-OR Implementation
Also known as technology-independent circuit.
INPUTS
AND OR C P1 F1 P2 A P3 F2 B P4 D
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

14. ELEC 7770: Advanced VLSI Design (Agrawal)
A NAND Implementation
INPUTS
NAND
NAND C F1 A F2 B D
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

15. A Simple Technology Mapping
NAND2 (3)
NAND2 (3) C
(2) F1 D
NAND3 (4)
NAND3 (4) B
(2) F2
NAND2 (3) A
Cost = 24
NAND2 (3)
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

16. Improved Design: Represent Circuit as a Directed Acyclic Graph (DAG)F1 A F2 B
Each node is a
NAND gate. D
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

17. Split DAG into Trees (Forest)C D F1 C B D A B F2 A D
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

18. Use Only Inverter and 2-Input NAND
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

19. Forest with NOT and 2-Input NANDC D F1 B C D A F2 B A D
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

20. Graph Matching from Library
OAI21 (4) D F1
(2)
Nodes inserted
For pattern matching B
NAND3 (4) C D
Cost = 22
NAND3 (4)
NAND2 (3) A F2 B
(2) A D
NAND2 (3)
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

21. Improved Technology Mapping
(2)
AOI21 (4) F1 D
NAND3 (4)
NAND3 (4) B
(2) F2
NAND2 (3) A
Cost = 22
NAND2 (3)
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)

22. ELEC 7770: Advanced VLSI Design (Agrawal)
References
G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.
S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994.
K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG Matching,” Proc. 24th Design Automation Conf., 1987, pp
Spring 14, Apr
ELEC 7770: Advanced VLSI Design (Agrawal)