HW/SW Interface Design

HW/SW Interface Design
최기영 (서울대학교, 전기컴퓨터공학부) Copyrightⓒ2003

과목 개요(Learning Map) SoC Design Methodoloy Design Flow Classes Lab.
Ÿ Soc Design Flow Introduction Ÿ Design Reuse & SoC Platform Specification Ÿ System Specification System Spec. Lab. Ÿ HW/SW Interface Design Ÿ Power Estimation & Management Design Design Language Lab. Ÿ DSM Design & Signal Integrity Ÿ Design Language Ÿ Synthesis Synthesis Ÿ Architecture Mapping Ÿ Verification Verification Ÿ HW/SW Co-simulation Co-simulation Lab. Ÿ Prototyping & Emulation Ÿ SoC Testing Test SoC Test Lab. Ÿ Design for Testability Copyrightⓒ2003

Outline Introduction On-Chip Buses Network-on-Chip Interface Design
SoC design On-chip communication architecture On-Chip Buses AMBA MicroNetwork Network-on-Chip Circuit switch network versus packet switch network Circuit switch network Packet switch network Interface Design Interface between HW modules and SW processes Communication wrapper design Interface SW design Interface design flow Interface Protocol Standards Interface standards VCI OCP AMBA AXI References Copyrightⓒ2003

Introduction DSP P1 P2 Bridge ASIC Mem. SoC design
Computation for functional blocks in the application HW modules SW running on processors Communication (interface) between HW modules and SW processes HW Buses/bridges or networks Wrappers Buffers or memories Decoders DMA controllers SW Device drivers Interrupt service routine OS Middleware Memory instructions DSP P1 P2 Bridge ASIC Mem. Copyrightⓒ2003

On-chip communication architecture
mP, DSP Local memory w/ I/D caches Application SW SW architecture Middleware HW IP OS Device drivers DMA Memory Processor local bus Comm. wrap. Comm. wrap. Comm. wrap. Communication network (OCBs w/ bridges, Sonics, packet/circuit switch, etc.) HW architecture Copyrightⓒ2003

Communication thru on-chip bus or on-chip network On-chip bus examples
AMBA Advanced High-performance Bus (AHB) (ARM Inc.) SiliconbackplaneTM III MicroNetwork (Sonics Inc.) On-chip network (or Network-on-Chip) examples Circuit-switch network: PROPHID (Philips Inc.) Packet-switch network: Torus, Octagon, Mesh (Aethereal (Philips)) Copyrightⓒ2003

On-Chip Buses AMBA [1] AMBA AHB: one of the most popular on-chip buses
Copyrightⓒ2003

AMBA AHB (Advanced High Performance Bus)
Pipelined operation Multiple bus masters Burst transfers Split transactions Central multiplexer interconnection scheme (cf. tri-state implementation) AHB interconnection Copyrightⓒ2003

Multi-layer AHB An interconnection scheme based on AHB protocol
Enables parallel access paths between multiple masters and slaves in a system. Copyrightⓒ2003

MicroNetwork [2] Sonics SiliconBackplane MicroNetwork On-chip bus
Time-division multiple access (TDMA) Copyrightⓒ2003

Pre-characterized agent timing in targeted flow
Agents placed near attached IP cores Distributed multiplexed bus structure with OR-tree repeaters Copyrightⓒ2003

Two-step arbitration Originally assigned modules  TDMA
If a slot has no bus access  priority-based Copyrightⓒ2003

Network-on-Chip Circuit switch network versus packet switch network [3] Circuit switch network Communication path is fixed before data transmission starts. Advantage QoS guaranteed Suit for real-time system Disadvantage Lower resource utilization Connection setup overhead Packet switch network Communication path is determined dynamically depending on network traffic. Better adaptation of communication to varying network traffic Better utilization of network resource Poor QoS Copyrightⓒ2003

Circuit switch network
Philips PROPHID architecture [4] Copyrightⓒ2003

Packet switch network Torus [5]
- Top 2 metal layers are used for the 2D folded torus topology. - Each tile can have processor, DSP, memory, I/O, etc. - 256bit data line Copyrightⓒ2003

Interface Design Interface between HW modules and SW processes
Interface between a HW module and a bus/network Called a communication wrapper May perform interface protocol conversion and/or system level buffering and caching SW interface Device drivers Interrupt service routine OS (communication services) Middleware Memory instructions Copyrightⓒ2003

Communication wrapper design
Wrapper architecture IP PA: Port adapter CA: Channel adapter PA PA PA PA External port Internal port Internal bus architecture CA CA Communication Wrapper Communication Network #1 Communication Network #2 Communication Network : AMBA, MicroNetwork, … Copyrightⓒ2003

Mux Port/Channel Adapters (Master) Port/Channel Adapter (Slave)
Wrapper internal bus architecture Internal Bus Arbiter Address Decoder MasterSel nREQ nGRNT enable Mux Port/Channel Adapters (Master) Port/Channel Adapter (Slave) External Port External Port Address Data_bus status Copyrightⓒ2003

Interface SW design Middleware: CORBA, COM+, JAVA, BREW
Service resolution ORB implementation Dynamic reconfiguration of services needs to be supported. baseband modem in HW --> Bluetooth in SW Operating system Communication services Pipe, shared memory, semaphore, mutex, etc. Supported as OS system calls Copyrightⓒ2003

Device driver and ISR Memory instructions
Device drivers depend on OS and processor OS Preemptive or not, interrupt or not, synchronization services (semaphore, lock var, …) Processor Bus width, register set, exception behavior, etc. Memory instructions Load/store, load multiple/store multiple instructions Cache/virtual memory instructions Copyrightⓒ2003

Physical Communication Network
Interface design flow Communication refinement Automatic generation of adapter architecture Channels M1 M3 M2 M1 M3 wrapper IP Internal Bus MA µP OS wrapper CA1 CA2 CA3 CA4 Physical Communication Network Copyrightⓒ2003

Interface generation flow [7]
Copyrightⓒ2003

Interface Protocol Standards
Interface standards VCI (Virtual Component Interface) Standardized by OCB DWG of VSIA OCP (Open Core Protocol) Proposed by Sonics Inc. A functional superset of VCI, adding configurable sideband control signaling and test harness signals AMBA AXI (AMBA Advanced eXtensible Interface) Proposed by ARM Inc. Backward-compatible with existing AHB and APB interface Copyrightⓒ2003

VCI [8] Virtual Component
Intellectual Property (IP) Standard by On Chip Bus Development Working Group (OCB DWG) of VSIA Goal Maximum portability No requirements of modification of VCs. Assumption Initiator/target connections are point-to-point Describes three difference interface standards Peripheral VCI Basic VCI Advanced VCI Copyrightⓒ2003

PVCI protocol Operation Type Read8, Read16, Read32, Read N cells
Write8, Write16, Write32, Write N cells Handshake protocol Copyrightⓒ2003

Handshake example: PVCI Read and Write
Copyrightⓒ2003

Cell, packet, packet chain
Cell: 1, 2, 4, 8, 16 bytes Packet: combined cells, which map a burst on a bus Packet chain: combined packets Command NOP (optional), Read, Write, Locked-Read(optional) Addressing Mode Random address mode Contiguous mode Wrap mode Constant Copyrightⓒ2003

Advanced VCI An Optimal extension of BVCI for multi-processor SoC
Incompatibility with BVCI Out-of-order transfer Advanced packet model Protocol Multi-thread transaction Arbitration hide mode added for AVCI Copyrightⓒ2003

OCP [9] Specification Point-to-Point synchronous interface
Bus independent Pipelined operation Separate requests from responses Burst operation Threads and virtual connections Interrupts, errors, and other sideband signaling Copyrightⓒ2003

AMBA AXI [10] Provide flexibility in the implementation of interconnect architectures Backward-compatible with existing AHB and APB interfaces Separate address/control and data phase Support unaligned data transfers using byte strobes Support out-of-order transaction completion Support low power operation Provide Interfaces between A master and the interconnect A slave and the interconnect A master and a slave Copyrightⓒ2003

Channel architecture Address channel Read channel Write channel
Variable-length burst Wrapping, incrementing, and non-incrementing bursts System-level caching and buffering control Secure and privileged access Read channel Data bus, which can be 8 ~ 1024 bits wide Read response for read completion Write channel One byte lane strobe for every 8 bits for indicating valid data Copyrightⓒ2003

References [1] AMBA 2.0 specification, http://www.amba.com
[2] SiliconBackplaneTM III MicroNetwork specification, [3] Axel Jantsch and Hannu Tenhunen, Networks on Chip, Kluwer academic publishers, 2003. [4] J. Leijten, J. van Meerbergen, A. Timmer, and J. Jess, “PROPHID: a heterogeneous multi-processor architecture for multimedia,” in Proc. International Conference on Computer Aided Design, 1997 [5] W. J. Dally and B. Towles, “Route packet, not wires: on-chip interconnection networks,” in Proc. Design Automation Conference, June 2001. [6] Faraydon Karim, Anh Nguyen, Sujit Dey, and Ramesh Rao, “On-chip communication architecture for OC-768 network processors,” in Proc. Design Automation Conference, June 2001. [7] W. CESARIO, Y. PAVIOT, A. BAGHDADI, L. GAUTHIER, D. LYONNARD, G. NICOLESCU, S. YOO, A.A. JERRAYA, M. DIAZ-NAVA, "HW/SW Interfaces Design of a VDSL Modem using Automatic Refinement of a Virtual Architecture Specification into a Multiprocessor SoC: a Case Study", DATE 2002, Paris, France, March 2002. [8] Virtual Component Interface Standard version 2 (OCB2 2.0), On-Chip Bus Development Working Group, April 2001, [9] Open Core Protocol specification version 2.0, 2003, [10]AMBA AXI protocol specification, ARM Inc. 2003, Copyrightⓒ2003

HW/SW Interface Design

Similar presentations

Presentation on theme: "HW/SW Interface Design"— Presentation transcript:

Similar presentations

About project

Feedback

Log in

Auth with social network:

HW/SW Interface Design

Similar presentations

Presentation on theme: "HW/SW Interface Design"— Presentation transcript:

Similar presentations

About project

Feedback