1. EE694v-Verification-Lect11
PS1 and PS2 Solutions
Solutions for PS1
Solution for PS2
EE694v-Verification-Lect11

2. EE694v-Verification-Lect11
PS1 Solution
The ENTITY for any soluiton
--=============================================================================
-- Generic Function Unit Entity
ENTITY generic_function IS
PORT (A,B,G3,G2,G1,G0 : IN BIT;
R : OUT BIT);
END generic_function;
This entity has all inputs at type BIT
EE694v-Verification-Lect11

3. EE694v-Verification-Lect11
PS1 ARCHITECTURE 1
A simple Boolean Equation
ARCHITECTURE one OF generic_function IS
BEGIN
R <= (NOT A AND NOT B AND G0) OR
(NOT A AND B AND G1) OR
( A AND NOT B AND G2) OR
( A AND B AND G3);
END one;
EE694v-Verification-Lect11

4. EE694v-Verification-Lect11
PS1 ARCHITECTURE 2
Conditional signal assignment statement solution
ARCHITECTURE two OF generic_function IS
BEGIN
R <= G0 after 15 ns WHEN A = '0' AND B = '0' ELSE
G1 after 15 ns WHEN A = '0' AND B = '1' ELSE
G2 after 15 ns WHEN A = '1' AND B = '0' ELSE
G3 after 15 ns ;
END two;
EE694v-Verification-Lect11

5. EE694v-Verification-Lect11
PS1 ARCHITECTURE 3
Selected signal assignment statement solution
ARCHITECTURE three OF generic_function IS
BEGIN
WITH A&B SELECT
R <= G0 WHEN “00”,
G1 WHEN “01”,
G2 WHEN “10”,
G3 WHEN “11”;
END one;
EE694v-Verification-Lect11

6. EE694v-Verification-Lect11
Simulation Results
Simulation results look like:
EE694v-Verification-Lect11

7. EE694v-Verification-Lect11
PS2 Solution
The carry chain
EE694v-Verification-Lect11

8. EE694v-Verification-Lect11
The slice
Declarative region
EE694v-Verification-Lect11

9. EE694v-Verification-Lect11
The slice
The statements
Instantiation
EE694v-Verification-Lect11

10. EE694v-Verification-Lect11
Simulation Results
PS2 results
EE694v-Verification-Lect11