1. EE2174: Digital Logic and Lab
CSE221: Logic Desing, Spring 2003
29-Dec-18
EE2174: Digital Logic and Lab
Professor Shiyan Hu
Department of Electrical and Computer Engineering
Michigan Technological University
CHAPTER 10
Sequential Logic Design
Chapter 1: Digtal Computers and Information

2. Sequential Circuit Analysis
Analysis: Consists of obtaining a suitable description that demonstrates the time sequence of inputs, outputs, and states.
Logic diagram: Boolean gates, flip-flops (of any kind), and appropriate interconnections.
The logic diagram is derived from any of the following:
Boolean Equations (FF-Inputs, Outputs)
State Table
State Diagram
Chapter 10: Sequential Logic Design

3. Chapter 10: Sequential Logic Design
Example 1
Input: x(t)
Output: y(t)
State: (A(t), B(t))
What is the Output Function?
What is the Next State Function? A C D Q y x B CP
Chapter 10: Sequential Logic Design

4. Chapter 10: Sequential Logic Design
Example 1 (continued)
Boolean equations for the functions:
A(t+1) = A(t)x(t) B(t)x(t)
B(t+1) = A’(t)x(t)
y(t) = x’(t)(B(t) + A(t)) x D Q A C Q A’
Next State D Q B CP C Q' y
Output
Chapter 10: Sequential Logic Design

5. State Table Characteristics
State table – a multiple variable table with the following four sections:
Present State – the values of the state variables for each allowed state.
Input – the input combinations allowed.
Next-state – the value of the state at time (t+1) based on the present state and the input.
Output – the value of the output as a function of the present state and (sometimes) the input.
From the viewpoint of a truth table:
the inputs are Input, Present State
and the outputs are Output, Next State
Chapter 10: Sequential Logic Design

6. Chapter 10: Sequential Logic Design
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Example 1: State Table
The state table can be filled in using the next state and output equations:
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) =A (t)x(t);
y(t) =x (t)(B(t) + A(t))
Present State
Input
Next State
Output
A(t) B(t)
x(t)
A(t+1) B(t+1)
y(t) 1
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

7. Example 1: The Other State Table
The other state table representation
A(t+1) = A(t)x(t) + B(t)x(t)
B(t+1) =A (t)x(t)
y(t) =x (t)(B(t) + A(t))
Present
State
Next State
x(t)= x(t)=1
Output
x(t)=0 x(t)=1
A(t) B(t)
A(t+1)B(t+1) A(t+1)B(t+1)
y(t) y(t)
0 0
0 1
1 0
1 1
Chapter 10: Sequential Logic Design

8. Chapter 10: Sequential Logic Design
State Diagrams
The sequential circuit function can be represented in graphical form as a state diagram with the following components:
A circle with the state name in it for each state
A directed arc from the Present State to the Next State for each state transition
A label on each directed arc with the Input values which causes the state transition, and
A label:
On each circle with the output value produced, or
On each directed arc with the output value produced.
Chapter 10: Sequential Logic Design

9. Chapter 10: Sequential Logic Design
State Diagrams
Label form:
On circle with output included:
state/output
Moore type output depends only on state
On directed arc with the output included:
input/output
Mealy type output depends on state and input
Chapter 10: Sequential Logic Design

10. Mealy Vs Moore machines
Mealy model:
Both outputs and next state depend both on primary inputs AND present state.
Moore model:
Only next state depends directly on primary inputs AND present state. Outputs depend only on present state.
Chapter 10: Sequential Logic Design

11. Canonical Sequential Circuit
Combinational
Network
s(t+1)
s(t)
State Register
next
state
present
state
x(t)
present
inputs
clock
z(t)
output
Chapter 10: Sequential Logic Design

12. Chapter 10: Sequential Logic Design
Mealy Machine C1 C2
s(t+1)
State Register
next
state
s(t)
x(t)
present
state
z(t)
present
inputs
clock
Chapter 10: Sequential Logic Design

13. Chapter 10: Sequential Logic Design
Moore Machine C2 C1
s(t+1)
z(t)
State Register
next
state
s(t)
present
state
x(t)
present
inputs
clock
Chapter 10: Sequential Logic Design

14. Example of Mealy Machine State Diagram
29-Dec-18
Example of Mealy Machine State Diagram
A B
0 0
0 1
1 1
1 0
x=0/y=1
x=1/y=0
x=0/y=0
Type: Mealy
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

15. Chapter 10: Sequential Logic Design
Example: Mealy model
State Table
Present State
Input
Next State
Output
A(t)
B(t) X
A(t+1)
B(t+1) Y 1
Possible states = { 00, 01, 10, 11 }
 4 nodes in state diagram
Chapter 10: Sequential Logic Design

16. Example: Mealy model (cont.)
State Diagram 00
0/0 01
1/0
I/O S1 S2
0/1
0/1
0/1 11
1/0
Reads as: When at state s1 and apply
input I, we get output O
and proceed to state s2. 10
1/0
1/0
Chapter 10: Sequential Logic Design

17. Chapter 10: Sequential Logic Design
Example: Moore model
State Table
Present State
Inputs
Next
State
Output
A(t) X Y
A(t+1) Z 1
Possible states = { 0, 1 }
 2 nodes in state diagram
Chapter 10: Sequential Logic Design

18. Example: Moore model (cont.)
State Diagram I
0/0
00,11
S1/O1
S2/O2
1/1
01,10
Reads as: When at state s1 with output
O1 and apply input I,
we proceed to state s2 with
Output O2.
01,10
00,11
Chapter 10: Sequential Logic Design

19. Moore and Mealy Example Diagrams
Mealy Model State Diagram maps inputs and state to outputs
Moore Model State Diagram maps states to outputs 1
x=1/y=1
x=1/y=0
x=0/y=0
1/0
2/1
x=1
x=0
0/0
Chapter 10: Sequential Logic Design

20. Moore and Mealy Example Tables
Mealy Model state table maps inputs and state to outputs
Moore Model state table maps state to outputs
Present
State
Next State
x=0 x=1
Output 1
Present
State
Next State
x=0 x=1
Output 1 2
Chapter 10: Sequential Logic Design

21. Example 2: Sequential Circuit Analysis
Logic Diagram:
Clock
Reset D Q C R A B Z
Chapter 10: Sequential Logic Design

22. Example 2: Flip-Flop Input Equations
29-Dec-18
Example 2: Flip-Flop Input Equations
Variables
Inputs: None
Outputs: Z
State Variables: A, B, C
Initialization: Reset to (0,0,0)
Equations
A(t+1) = B(t)C(t)
B(t+1) = B’(t)C(t)+B(t)C’(t)
C(t+1) = A’(t)C’(t)
Z(t) = A(t)
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

23. Chapter 10: Sequential Logic Design
29-Dec-18
Example 2: State Table
A(t) B(t) C(t)
A(t+1) B(t+1) C(t+1)
Z(t)
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 0
0 0 0 1
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

24. Example 2: State Diagram
29-Dec-18
Example 2: State Diagram
000
011
010
001
100
101
110
111
Reset
ABC
Which states are used?
What is the function of the circuit? 000 -> 001 -> 010 -> 011 -> 100 -> 000 -> 001 -> 010 -> 011 -> 100 …
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

25. The Sequential Circuit Design Procedure
Specification
Formulation - Obtain a state diagram or state table
State Assignment - Assign binary codes to the states
Flip-Flop Input Equation Determination - Select flip-flop types and derive flip-flop equations from next state entries in the table
Output Equation Determination - Derive output equations from output entries in the table
Optimization - Optimize the equations
Technology Mapping - Find circuit from equations and map to flip-flops and gate technology
Verification - Verify correctness of final design
Chapter 10: Sequential Logic Design

26. Sequence Recognizer Procedure
To develop a sequence recognizer state diagram:
When it reads a specified sequence, the circuit outputs 1 and 0 otherwise.
Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically “reset” state).
Add a state that recognizes that the first symbol has occurred.
Add states that recognize each successive symbol occurring.
The final state represents the input sequence (possibly less the final input value) occurrence.
Add state transition arcs which specify what happens when a symbol not in the proper sequence has occurred.
Add other arcs on non-sequence inputs which transition to states that represent the input subsequence that has occurred.
The last step is required because the circuit must recognize the input sequence regardless of where it occurs within the overall sequence applied since “reset”.
Chapter 10: Sequential Logic Design

27. Sequence Recognizer Example
Example: Recognize the sequence 1101
Note that the sequence contains 1101 and "11" is a proper sub-sequence of the sequence.
Thus, the sequential machine must remember that the first two one's have occurred as it receives another symbol.
Also, the sequence contains 1101 as both an initial subsequence and a final subsequence with some overlap, i. e., or
And, the 1 in the middle, , is in both subsequences.
The sequence 1101 must be recognized each time it occurs in the input sequence.
Chapter 10: Sequential Logic Design

28. Chapter 10: Sequential Logic Design
Example: Recognize 1101
Define states for the sequence to be recognized:
assuming it starts with first symbol,
continues through each symbol in the sequence to be recognized, and
uses output 1 to mean the full sequence has occurred,
with output 0 otherwise.
Starting in the initial state (Arbitrarily named "A"):
Add a state that recognizes the first "1.“
State "A" is the initial state, and state "B" is the state which represents the fact that the "first" one in the input subsequence has occurred. The output symbol "0" means that the full recognized sequence has not yet occurred. A B
1/0
Chapter 10: Sequential Logic Design

29. Example: Recognize 1101 (continued)
After one more 1, we have:
C is the state obtained when the input sequence has two "1"s.
Finally, after 110 and a 1, we have:
Transition arcs are used to denote the output function (Mealy Model)
Output 1 on the arc from D means the sequence has been recognized
To what state should the arc from state D go? Remember: ?
Note that D is the last state but the output 1 occurs for the input applied in D. This is the case when a Mealy model is assumed. A B
1/0 C
1/0 A B
1/0 C
0/0 D
1/1
Chapter 10: Sequential Logic Design

30. Example: Recognize 1101 (continued)B
1/0 C
0/0 D
1/1
Clearly the final 1 in the recognized sequence is a sub-sequence of It follows a 0 which is not a sub-sequence of Thus it should represent the same state reached from the initial state after a first 1 is observed. We obtain:
1/1 D A B
1/0 C
0/0
Chapter 10: Sequential Logic Design

31. Example: Recognize 1101 (continued)
1/1 A B
1/0 C D
0/0
The state has the following abstract meanings:
A: No proper sub-sequence of the sequence has occurred.
B: The sub-sequence 1 has occurred.
C: The sub-sequence 11 has occurred.
D: The sub-sequence 110 has occurred.
The 1/1 on the arc from D to B means that the last 1 has occurred and thus, the sequence is recognized.
Chapter 10: Sequential Logic Design

32. Example: Recognize 1101 (continued)
The other arcs are added to each state for inputs not yet listed. Which arcs are missing?
Answer:
"0" arc from A "0" arc from B "1" arc from C "0" arc from D.
1/0
1/0
0/0 A B C D
1/1
Chapter 10: Sequential Logic Design

33. Example: Recognize 1101 (continued)
State transition arcs must represent the fact that an input subsequence has occurred. Thus we get:
Note that the 1 arc from state C to state C implies that State C means two or more 1's have occurred.
0/0
1/0
1/1 A B
1/0 D
0/0 C
0/0
0/0
Chapter 10: Sequential Logic Design

34. Formulation: Find State Table
From the State Diagram, we can fill in the State Table.
There are 4 states, one input, and one output. We will choose the form with four rows, one for each current state.
From State A, the 0 and 1 input transitions have been filled in along with the outputs.
1/0
0/0
1/1 A B C D
0/0 A
1/0 B
Present
State
Next State
x=0 x=1
Output A B C D
Chapter 10: Sequential Logic Design

35. Formulation: Find State Table
From the state diagram, we complete the state table.
1/0
0/0
1/1 A B C D
State
Present
Next State
x=0 x=1
Output
x=0 x=1 A
A B B
A C C
D C D
Chapter 10: Sequential Logic Design

36. State Assignment (Version 1)
29-Dec-18
State Assignment (Version 1)
Assignment 1: A = 00, B = 01, C = 10, D = 11
The resulting coded state table:
Present State
Input
Next State
Output
D1(t) D2(t)
x(t)
D1(t+1) D2(t+1)
z(t) 1
Present State
Next State
x = 0 x = 1
Output
0 0
0 1
1 0
1 1 1
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

37. State Assignment (Version 2)
29-Dec-18
Assignment 2: A = 00, B = 01, C = 11, D = 10
The resulting coded state table:
Present State
Next State
x = 0 x = 1
Output
0 0
0 1
1 1
1 0 1
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

38. Chapter 10: Sequential Logic Design
Optimization Version 1
Performing two-level optimization:
D1 (t+1)= D1D2’ + XD1’D2 D2 (t+1)= XD1’D2’ + XD1D2 + X’D1D2’ Z (t)= XD1D2’ Gate Input Cost = 22
D1(t+1)
D2(t+1)
Z(t) D2 D1 X 1 D2 D1 X 1 D2 D1 X 1
Chapter 10: Sequential Logic Design

39. Chapter 10: Sequential Logic Design
Optimization Version 2
Performing two-level optimization:
D1 (t+1)= D1D2 + XD Gate Input Cost = 9 D2 (t+1)= X Slect this state assignment for Z (t)= XD1D2’ completion of the design
D1(t+1)
D2(t+1)
Z(t) D2 D1 X 1 D2 D1 X 1 D2 D1 X 1
Chapter 10: Sequential Logic Design

40. Chapter 10: Sequential Logic Design
29-Dec-18
Map Technology
Library:
D Flip-flops with Reset
NAND gates with up to 4 inputs and inverters
Initial Circuit
Clock D C R D2 Z D1 X
Reset
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

41. Chapter 10: Sequential Logic Design
29-Dec-18
Mapped Circuit
Clock D C R D2 Z D1 X
Reset
Chapter 10: Sequential Logic Design
Chapter 4: Sequential Circuits (Sections )

42. Chapter 10: Sequential Logic Design
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Chapter 10: Sequential Logic Design