1. Circuit Characterization and Performance Estimation
Chapter 4
Circuit Characterization and Performance Estimation

2. Effective Resistance and Capacitance
In the worst case, there is only one PMOS “ON”.
Thus, two unit width have resistance R.
R/3

3. Diffusion Capacitance Layout Effects

4. Elmore Delay Model

5. Example
Tpdr=R*((6+4h)C)
Tpdf=R/2*2C+R*((6+4h)C)

6. Logical Effort
Logical effort: The ratio of the input capacitance of the gate
to the input capacitance of an inverter
HW: EXERCISE 4.19

7. 3 units of diffusion capacitance on the output, defined 1
Parasitic Delay
3 units of diffusion capacitance on the output, defined 1
6 units of diffusion capacitance on the output, normalized with INVERTER

8. Gate-Source Capacitance
Tpdf=R/2*(2C+2C)+R*((6+4h)C)

9. f=g (logical effort)*h
Linear Delay Model
d (propagation delay)
=f (stage effort)+p (parasitic delay)
f=g (logical effort)*h
h=4/1
h=Cout/Cin
d=gh+p=1* 4 +1 =5
HW: EXERCISE 4.21
HW: EXERCISE 4.5

10. Delay in multistage Logic

11. Example

12. Example G=1*1=1 H=90/5=18 F=f1*f2=g1h1*g2h2 =1*(90/15)*1*(90/15) =36
b=(15+15)/15=2

13. Example B=3*2=6 G=(4/3)*(5/3)*(5/3)=100/27 H=45/8 F=BGH=125 P=2+3+2=7
The best stage effort
=^f=1251/3=5
D=N (N-stage)*^f+P
=3*5+7=22
y=Cout*g/^f=45*(5/3)/5=15
x=Cout*g/^f=(15+15)*(5/3)/5=10
A=Cout*g/^f=( )*(4/3)/5=8

14. Example 10 15 8 y=Cout*g/^f=45*(5/3)/5=15
x=Cout*g/^f=(15+15)*(5/3)/5=10
A=Cout*g/^f=( )*(4/3)/5=8

15. Choosing the Best Number of Stages
P=N*1
B=1
H=64/1=64
G=1
F=BGH=64
The best stage effort
=^f=F1/N=641/N
D=N*^f+P
HW: EXERCISE 4.10

16. Best Number of Stages Let
After iteration, the best stage effort is e ( ).
HW: EXERCISE 4.24 (ρ=4)

17. Pstatic_total=130 W*(31+24)=7.2 mW
Static Dissipation
Example
=73 A
=130 W
Pstatic_total=130 W*(31+24)=7.2 mW
Pstatic=IstaticVDD

18. Dynamic Dissipation Pdynamic=*α*CVDD2fsw Activity factor Example
Clogic= 24 nF, Cmemory= 72 nF
Example
Pdynamic_total=(0.1*24n+0.05*72n)*1.22
=8.6 mW/MHz
= 8.6
HW: EXERCISE 4.27

19. Power Reduction
Device-switching capacitance is reduced by choosing small transistors.
Choosing a lower power supply significantly reduced power supply.
Clock gating can be used to stop portions of the chip that are idle.
Reducing leakage current when the chip is idle.
HW: EXERCISE 4.28

20. Resistance

21. Capacitance
Cgnd=Cbot+Ctop
Ctotal=Cgnd+2Cadj

22. Delay Example 5mm long,0.32 um wide metal2 5000/0.32=15625 
15625  * 0.05 /=781 
0.2fF/m * 5000 m=1 pF
HW: EXERCISE 4.30

23. Inductance

24. Reduce Inductance

25. Wire engineering
Width and spacing
Layer selection
Shielding
Repeaters

26. Pitches and Spacings

27. Low-resistance layer for fast and critical signals is chosen.
Layer selection
Low-resistance layer for fast and critical signals is chosen.

28. Shielding
Very sensitive signals such as clock and analog signals must be shieled.

29. Repeaters

30. Crosstalk

31. Reduce crosstalk

32. Design Margin Supply voltage (10%) Operating temperature
Process variation

33. Design Corners

34. Latchup A larger current flowing between VDD and GND that persists
until the power supply is turned off or the power wires melt.
Minimize Rsub and Rwell to prevent latchup

35. Scaling

36. Scaling MOS Devices

37. Romap of Predictions