1. HaRDROC status: (Hadronic RPC Detector Read Out Chip for DHCAL)
IN2P3/LAL+IPNL+LLR R. GAGLIONE, I. LAKTINEH, H. MATHEZ IN2P3/IPNL LYON M. BOUCHEL, R. CHICHE, J. FLEURY, C. de LA TAILLE, G. MARTIN-CHASSARD, N. SEGUIN-MOREAU IN2P3/LAL ORSAY J.C. BRIENT, C. JAUFFRET IN2P3/LLR PALAISEAU

2. HaRDROC architecture Only one serial output @ 5MHz Full power pulsing
Digital memory: Data saved during bunch train.
Only one serial 5MHz
Store all channels and BCID for every hit. Depth = 128 bits
Data format : 128(depth)*[2bit*64ch+24bit(BCID)+8bit(Header)] = 20kbits
Based on MAROC ASIC, but several design changes
05 April 07
HARDROC LAL ORSAY

3. HARDROC1: TESTBOARD with a packaged chip
3 packaged ASICs, 10 naked dies received in january 07
70 naked dies received in March 07
7 testboards
05 April 07
HARDROC LAL ORSAY

4. HARDROC1: TESTBOARD with Chip On Board
05 April 07
HARDROC LAL ORSAY

5. SS and BFS waveforms (scope measurements)
DC level
≈ 2V
100fC
Bip. Fast Sh (BFS)
Slow Shaper (SS)
10 pC
BFS: 100fC => 350mV, tp=15ns, ie 3.5mV/fC
SS: 10 pC => 535mV, tp=150 ns
1pC
DC level
≈ 1V
05 April 07
HARDROC LAL ORSAY

6. SS measurements (scope)
Qinj=100 fC :
Gain PA= mV tp=144 ns
G= mV ns
G= mV ns
G= mV ns
05 April 07
HARDROC LAL ORSAY

7. DC meas. of FSB and SS: Uniformity
<>=2V, σ=1.3mV
<>=1.10V σ=1.8mV
05 April 07
HARDROC LAL ORSAY

8. HARDROC1: Integrated DACs linearity
2 integrated DACs to deliver Threshold voltages
Residuals within ±5 mV / 2.6V dynamic range. INL= 0.2% (2LSB)
2.5 mV/UDAC
05 April 07
HARDROC LAL ORSAY

9. Zin and Xtk Zin (PA)=50Ω with Vgain=3V, Zin (PA)=70Ω with Vgain=3.5V
Qinj=100fC on Ch7
out_fsb=160mV (on 50Ω), tp=15ns
Xtk: well differentiated
Ch6: ± 3mV
Ch8: ± 3mV (± 2%)
Ch9: ± 0.5mV
Xtk: on the input
Gain=1 on Ch7 and Gain=0 on Ch8,
=> Xth (ch8)=0
Ch7
Xtk Ch8 *10
Discri out/10
Scope, 50Ω)
05 April 07
HARDROC LAL ORSAY

10. Trigger: Trigger down to 10 fC Time walk 05 April 07
HARDROC LAL ORSAY

11. Trigger Xtk: DAC0 and DAC1= 300 (=> Vth0 =Vth1~50fC) Qinj in Ch7
1.6 pC: triggers on CH7 only, nothing on the neighbors
1.8 pC: Triggers on Ch7 and CH6, no trig on other channels
2 pC up to 5,6pC: Triggers on CH7, CH6 and 8
10pC Triggers on Ch7 and on the 4 direct neighbors.
05 April 07
HARDROC LAL ORSAY

12. Trigger efficiency: Scurves
Vth0=180 (~2.1V)
Vth0=350 (~1.65V)
DC=2V equivalent
to DAC=240
Pedestal
Pedestal
Trigger
Efficiency
Vth0
05 April 07
HARDROC LAL ORSAY

13. Scurves, Gain PA=1 and 4 Gain=1 Gain=1 Pedestal Qin=100fC Gain=4
Piedestal
Qin=10fC
Qinj=10fC
05 April 07
HARDROC LAL ORSAY

14. HARDROC1: digital part
05 April 07
HARDROC LAL ORSAY

15. MEMORY FRAMES Dout_007 is displayed on the scope.
CK used for the readout: 1.25MHz
!1st frame: irrelevant
SETUP:
DAC0=800
=>Vth0=660mV
=> RS_trig0=0
DAC1=0
=>Vth1=2.60V
=> RS_trig1=1
2nd frame:
Header (8bits), then BCID (24bits),
then 128 bits for trig0<0-63> and trig1<0-63>
05 April 07
HARDROC LAL ORSAY

16. MEMORY FRAMES: Auto trigger mode
Qinj=100fC in Ch7
DAC0 and DAC1=300 (~50fC)
Ch7
BCID
Header
05 April 07
HARDROC LAL ORSAY

17. Digital architecture towards 2nd generation DAQ
ECAL, AHCAL, DHCAL
Slab FE
FPGA
PHY
Data
Clock+Config+Control
VFE
ASIC
Conf/
Clock
detector readout
RamFull
BOOT CONFIG
FE-FPGA
Data Format
Zero Suppress
Protocol/SerDes
FPGA Config/Clock Extract
Clock
Clk
VFE ASIC
Bunch/Train Timing
Config Data
1G/100Mb Ethernet PHY
ADC
Data
05 April 07
HARDROC LAL ORSAY

18. 8x32 pads: RPC and µMegas RPC
6 PCBs (4chips): will be delivered the 24th of April
Tests with cosmics (standalone USB DAQ) in LLR +IPNL in June
Tests in July07 with test beam at DESY and CERN with DAQ0
Can be used for DAQ2 tests (UK)
8 layer PCB
FPGA
4 areas of 64 pads of 1 sq cm : bottom layer
Hardroc external components : top layer
05 April 07
HARDROC LAL ORSAY

19. 1m2 prototype: 96x48x2 pads Autumn 07, paid by CALICE, tests with DAQ0
Possibly 1 PCB
(1FPGA, 1 UK connector)
6x8x2=96cm
Autumn 07, paid by CALICE, tests with DAQ0
DAQ2 ?
1m (ANR DHCAL or ?)
05 April 07
HARDROC LAL ORSAY

20. Summary Analog part of hardroc1: preliminary measurements OK
Discriminate down to 10fC
No Xtk up to 1.6 pC (Vth=50 fC)
Power pulsing still to be tested
Digital part:
Looks OK for one chip
Lot of work to be done for the readout of several chips with DAQ0 and DAQ2
1 testboard already in London (Matt Noy),1 board in LLR, 1 board for Lyon
Production of 6 DHCAL prototype PCBs
PCB received the 24th of April
Components: in hand except packaged ASICs
Hardroc chips : 70 more bought, need packaging (200 €/chip!)
Manpower for test program and for measurements
05 April 07
HARDROC LAL ORSAY