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V.Navaneethakrishnan Dept. of ECE, CCET
VLSI Lay-out Design V.Navaneethakrishnan Dept. of ECE, CCET
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VLSI DESIGN Custom Design Semi-Custom Design Standard Cell Gate Array
Programmable Devices PLA/PAL CPLD FPGA SOC
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Fabrication Process begins with silicon wafers basically formed out of sand
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A series of process steps, including
epitaxial growth, dielectric and metal layer depositions, oxidation, diffusion, ion implantation and several steps of Lithography …. then follow
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……………………………………… ……………………………………… ……………………………………… ……………………………………… 1. 2.
3. Substrate p Thick oxide (1m) ……………………………………… ……………………………………… p Photoresist ……………………………………… ……………………………………… p
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……………………………………… ……………………………………… ……………………………………… 4. 5. UV light Mask
p Window in oxide ……………………………………… ……………………………………… p
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……………………………………… ……………………………………… ……………………………………… ……………………………………… …………
6. 7. ……………………………………… Patterned Poly. (1-2 m) On thin oxide ( A0 ) ……………………………………… ……………………………………… ……………………………………… p n+ diffusion (1 m deep) ………… ………… ……………………………………… ……………………………………… …… …… p
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…… ………… …… ………… …… …… ……. ………… ………… ………… ………… …… ………… …… …………
8. …… ………… …… ………… …… …… ……. ………… ………… ………… ………… Contact holes (cuts) …… ………… …… ………… ……………………………………… ……………………………………… p 9. …… ………… …… ………… …… …… ……. Patterned Metallization (aluminum 1 m) ………… ………… ………… ………… …… ………… …… ………… ……………………………………… ……………………………………… p
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Drain-to-source current Ids versus voltage Vds relationship
nMOS Transistor structure: Gate Drain W D Source L Charge induced in channel (Qc) Electron transit time() Ids = Isd = (1) Length of channel (L) Velocity(v) sd = First, transit time:
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Pass transistor And gate :
VDD X A B C X = A.B.C (Logic 1 = VDD – Vt ) nMOS inverter : Vin Vout VDD GND
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nMOS depletion mode transistor pull-up and transfer characteristic
Vout Vt Vin Vout VDD GND No current Current flows Non-zero output Vin
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4. Complementary transistor pull-up (CMOS) :
No current flow either for logical 0 or for logical 1 inputs. Full logical 1 and 0 levels are presented at the output. For devices of similar dimensions the p-channel is slower than the n-channel device. Vout Vtn Vtp VDD VDD p (ii) Transfer characteristic p on n off Vout both on Vin n p off n on Vin VSS VSS VDD (i) Circuit Regions Current (between ralls) 1 2 3 4 5 (iii) CMOS inverter Current versus Vin Vin
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An improved BiMOS inverter using MOS transistors for base current discharge
VDD T4 T2 Vin T5 Vout T3 T1 CL T6 GND VSS
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… … ……………………………………… …… ………… …… 1. 2. SiO2 p-well (4-5 m) Thin oxide
Polysilicon 2. …… ………… …… Thin oxide and polysilicon p n
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…… ………… …… …… ………… …… 3. 4. P+ mask (positive) P+ mask (negative)
p-diffusion P+ mask (positive) 3. …… ………… …… p n P+ mask (negative) n-diffusion 4. …… ………… …… p n
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CMOS p-well inverter showing VDD and VSS substrate connections
Polysilicon Oxide n-diffusion P-diffusion Vin Vout VDD VSS p n CMOS p-well inverter showing VDD and VSS substrate connections
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CMOS n-well inverter showing VDD and VSS substrate connections
Polysilicon Oxide n-diffusion P-diffusion Vin Vout VDD VSS n p CMOS n-well inverter showing VDD and VSS substrate connections
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( A logical extension of the p-well and n-well)
Polysilicon Oxide n-diffusion P-diffusion Vin Vout VDD VSS Epitaxial layer n well p well n substrate Twin-tub structure ( A logical extension of the p-well and n-well)
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Encodings for a simple single metal nMOS process
Stick diagram Encodings for a simple single metal nMOS process COLOR STICK ENCODING LAYERS MASK LAYOUT ENCODING CIF LAYER MONOCROME GREEN RED BLUE BLACK GRAY n-diffusion n+active Thniox Polysilicon Metal 1 Contact cut Overglass NOT APPLICABLE nMOS ONLY YELLOW Implant Buried contact nMOS ONLY BROWN ND NP NM NC NG NI NB
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Lamda-based design rules
Minimum separation Minimum width n-diffusion p-diffusion 2 3 2 1 1 2 2 Metal 1 Minimum width 2 3 3 Metal 2 3 4 4 4
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Transistor design rules
nMOS (enhancement) pMOS (enhancement) nMOS (depletion) Separation from contact cut to transistor Implant for an nMOS depletion mode transistor to extend 2 minimum beyond channel in all directions 2 minimum Separation from implant to another transistor 2 minimum
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Stick diagram and layout for nMOS shift register cell
Lamba VDD 25 20 4:1 15 2:1 10 GND 5 2 2 2 5 10 15 20 25 Lamba
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Stick diagram and layout for nMOS shift register cell
Lamba VDD 25 20 4:1 15 2:1 10 GND 5 2 2 2 5 10 15 20 25 Lamba
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Two way selector with enable
X O/P Y A A’ E X O/P Y A A’ E
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Thank You !!!
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