1. Fields in the FALCON-A Instruction
RTL naming operator
opá4..0ñ := IRá15..11ñ:operation code field
raá2..0ñ := IRá10..8ñ: target register field
rbá2..0ñ := IRá7..5ñ: operand or address index
rcá2..0ñ := IRá4..2ñ: second operand
c1á4..0ñ := IRá4..0ñ: short displacement field
c2á7..0ñ := IRá7..0ñ: long displacement or
immediate field

2. Review

3. CS501 Advanced Computer Architecture
Lecture09
Dr.Noor Muhammad Sheikh

4. Describing the Processor State Using RTL
PC<15..0>: program counter
(memory address of next instruction)
IRá15..0ñ: instruction register
Run: one bit run/halt indicator
Strt: start signal
R[0..7]á15..0ñ: general purpose registers

5. Using RTL to Describe the Dynamic Properties of the FALCON-A
Conditional expressions, e.g.
(op=2) : R[ra] ¬ R[rb] - R[rc];
IF condition
; is an RTL termination operator
RTL assignment operator
THEN perform this action

6. Effective Address Calculations in RTL (Performed At Runtime)
Displacement Address
dispá15..0ñ := ( R[rb] + ( 11 α C1<4> ) © C1<4..0> );
Relative Address
relá15..0ñ := PC + ( 8 α C2<7> ) © C2<7..0>;
Sign Extension
Sign Extension

7. Range of Memory Addresses
Using Direct Addressing (Displacement with rb=0)
If c1á4ñ=0 (positive displacement) absolute addresses range: 00000b to 01111b (0 to +15)
If c1á4ñ=1 (negative displacement) absolute addresses range: 11111b to 10000b (-1 to -16)
Using Relative Addressing
The largest positive value of C2á7..0ñ is 27-1 and its most negative value is -27, so addresses up to 127 locations forward and 128 locations backwards from the current PC value can be specified

8. Instruction Fetch Operation (using RTL)
PC incremented by a value 2 because each instruction is 2 bytes long
instruction_Fetch := (
!Run & Strt : Run ¬ 1,
Run : (IR ¬ M[PC], PC ¬ PC + 2;
instruction_execution) );

9. appropriate processing goes in this place
Flow diagram
Instruction Fetch
Instruction Decode …
Op-code = 31
Op-code = 0
appropriate processing goes in this place
Op-code = 30
Op-code = 1 …

10. Instruction Execution (Jump Instructions)
ie := (
(op<4..0> = 20) : ( cond : PC ¬ R[ra] + c2(sign extended) ),
unconditional branch (jump)
(op<4..0> = 16) : cond : ( PC ¬ PC + C2(sign extended) ),
conditional jump (jpl)

11. Instruction Execution (Arithmetic and Logical Instructions)
ie := (
(op<4..0>=0) : R[ra] ¬ R[rb] + R[rc],
(op<4..0>=1) : R[ra] ¬ R[rb] + (11α C1<4>) © C1<4..0>,
(op<4..0>=2) : R[ra] ¬ R[rb] - R[rc],
(op<4..0>=3) : R[ra] ¬ R[rb] - (11 α C1<4>) © C1<4..0>,
(op<4..0>=4) : R[ra] ¬ R[rb] * R[rc],
(op<4..0>=5) : R[ra] ¬ R[0] © R[rb] / R[rc],
R[0] ¬ R[0] © R[rb] % R[rc],
(op<4..0>=8) : R[ra] ¬ R[rb] & R[rc],
(op<4..0>=10) : R[ra] ¬ R[rb] ~ R[c],
(op<4..0>=14) : R[ra] ¬ !R[rc],

12. Instruction Execution (Shift Instructions)
ie := (
(op<4..0>=12) : R[ra]á15..0 ñ ¬ R[rb]<( 15 – N )..0> © ( N α 0 );
(op<4..0>=13) : R[ra]á15..0 ñ ¬ ( N α 0 ) © R[rb]<15..N>;
(op<4..0>=15) : R[ra]á15..0 ñ ¬ N α ( R[rb]<15> ) © ( R[rb]<15..N> );
Shift Right
Shift Left
Arithmetic Shift Right
Notation: α means replication
© means concatenation

13. Instruction Execution (Data Transfer Instructions)
ie := (
(op<4..0>=29) : R[ra] ¬ M[R[rb] + (11 α C1<4>) © C1<4..0>];
(op<4..0>=28) : M[R[rb] + (11 α C1<4>) © C1<4..0>] ¬ R[ra];
(op<4..0>=6) : R[ra] ¬ R[rb];
(op<4..0>=7) : R[ra] ¬ (8 α C2<7>) © C2<7..0>;
(op<4..0>=24) : R[ra] ¬ IO[c2];
(op<4..0>=25) : IO[c2] ¬ R[ra];
load
store
mov
movi
out in

14. Instruction Execution (Miscellaneous Instructions)
ie := (
(op<4..0>= 21) : , (op<4..0>= 31) : Run ¬ 0, ); iF );
nop
halt
Instruction Execution ends here