1. Introduction to Micro Controllers & Embedded System Design Stored Program Machine
Department of Electrical & Computer Engineering Missouri University of Science & Technology
A.R. Hurson

2. Introduction to Micro Controllers & Embedded System Design
Note, this unit will be covered in three to four lectures. In case you pre-test it, then you have the following options: 1) Take the early test and start module3 2) Study the supplement module (supplement.module2) 3) Act as a helper to help other students in studying module1 Note, options 2 and 3 have extra credits as noted in course outline.
A.R. Hurson

3.   Introduction to Micro Controllers & Embedded System Design
Enforcement of background
Glossary of prerequisite topics No
Familiar with the topics?
Review background for this module
Yes
Take Test
At the end: take exam, record the score, impose remedial action if not successful No
Pass?
Remedial action 
Yes
Glossary of topics
Current Module No
Familiar with the topics?
Take the Module
Yes
Take Test No
Pass?
Yes
Options
Lead a group of students in
this module (extra credits)?
Study next module?
Study more advanced related topics (extra credits)?
A.R. Hurson
Extra Curricular activities

4. Stored Program Machine: A computer with a storage component that may contain both data to be manipulated and instructions to manipulate the data is called a stored program machine. This simply implies that the user is able to change the sequence of operations on the data.
Program: The sequence of operations performed on the data is called a program. More formally, it is a finite set of instructions that specify the operands, operations, and the sequence by which processing has to occur.
A.R. Hurson

5. Instruction: An instruction is a group of bits that tells the computer to perform a specific operation. It is composed of two parts:
Operation part
Operand part
A.R. Hurson

6. Operation part (operation code) is a group of bits that defines the action to be performed.
For each machine the set of operations is limited and defined.
In general, a machine with n bits as op.code is capable of supporting 2n distinct operations each having a distinct encoding as op.code.
A.R. Hurson

7. Operand part defines the element (s) needed for operation.
Within the scope of a program, besides the op.code, one needs four pieces of information (note majority of operations are binary operations):
2 operands as sources
1 operand as a destination
1 operand to specify the location of the next instruction that should be fetched.
A.R. Hurson

8. Depending on how many of these pieces of information are explicitly defined, instructions are grouped into 5 classes: 4, 3, 2, 1, and 0-address instructions.
A.R. Hurson

9. ADD A Accumulator is in implied mode.
The way in which operands are specified in an instruction is called the addressing mode. The ability to specify operands in different ways brings a greater degree of flexibility to the computer.
Implied Mode: In this mode operand(s) is(are) specified implicitly in the definition of instruction.
ADD A Accumulator is in implied mode.
Immediate Mode: In this mode operand value is defined in the instruction.
ADD 5
A.R. Hurson

10. Index Mode: In this mode address of the operand is determined by two values:
Contents of the index register
Displacement
Effective address - i.e., address of operand, is determined by adding the contents of index register to the displacement. Index mode is very effective when handling arrays, tables, …
Register Mode: In this mode operand value is contained in a register which is referenced to by the instruction. Usually, such a mode is used in the system with multiple registers.
ADD R1 To R2
A.R. Hurson

11. Direct Addressing Mode: In this mode the address of operand is explicitly defined in the instruction.
ADD A TO B
Indirect Mode: In this mode, the address of the address of operand value is contained in the instruction. Therefore, one needs two fetches to memory in order to retrieve the operand value.
ADD Aindirect TO B
Multilevel of Indirections: This is an extension of indirect mode, in which instruction contains the address of the address of the ... of operand.
A.R. Hurson

12. Direct Mode: Indirect Mode:
Main Memory
ADD A A
Direct Mode:
ADD A A B
Indirect Mode:
Main Memory
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13. + Index Mode: ADD 2, A 00 Main Memory 01 10 Index Registers
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14. A variation of index mode is called base addressing which allows re-locatibility.
Some systems allow a mixture of several addressing modes, i.e., indirect-register mode.
A.R. Hurson

15. Flow of Control and Data
1) Program and data are read in and stored in main memory.
2) An instruction is fetched from main memory.
3) Fetched instruction is decoded and investigated.
4) Operand(s) is(are) fetched.
5) Operation is performed.
6) Steps 2-5 are repeated up to the end of program.
A.R. Hurson

16. Flow of Control and Data
Steps 2-5 are called the instruction cycle.
Program counter is used to fetch an instruction.
Usually steps 2 and 3 are called instruction fetch cycle and steps 4 and 5 are called instruction execute cycle.
In order to execute a program, the system goes into a sequence of instruction cycles. Within each cycle an instruction is fetched, decoded, and executed.
A.R. Hurson

17. Introduction to Micro Controllers & Embedded System Design
Simple instruction cycle
Fetch/Decode/Execute sub-cycles
Each state may take one or several clock cycle(s)
Fetch
Decode
Execute
Each state lasts for one clock cycle. During the fetch state the current instruction is fetched from code memory and loaded into the instruction register. During the decode state the instruction is decoded and any required operands are fetched from memory or from the register file. During the execute state the instruction is executed. A result may be stored in a register or the accumulator updated. All three states constitute what is often called an instruction cycle.
A processor designer is interested in reducing the number of states and in how fast the state machine can be clocked since both determine the speed of the processor. It’s no good to have a very high clock rate if it takes a large number of states per instruction.
Questions:
1. Draw a timing diagram showing a clock, the current state, and next state for at least two instruction cycles.
2. Describe what needs to be done to implement the state machine controller in hardware
A.R. Hurson

18. Introduction to Micro Controllers & Embedded System Design
During the fetch state the current instruction is fetched from code memory and loaded into the instruction register.
During the decode state the instruction is decoded and any required operands are fetched from memory or from the register file.
During the execute state the instruction is executed. A result may be stored in a register or the accumulator updated. All three states constitute what is often called an instruction cycle.
A.R. Hurson

19. Introduction to Micro Controllers & Embedded System Design
A processor designer is interested in reducing the number of states and in how fast the state machine can be clocked since both determine the speed of the processor. It is no good to have a very high clock rate if it takes a large number of clocks per instruction.
A.R. Hurson

20. In order to execute a program, the system goes into a sequence of instruction cycles. Within each cycle an instruction is fetched, decoded, and executed.
What if an unexpected event happens during the execution of a program (during an instruction cycle)? For example, the system is instructed to perform division and the divisor is zero?
A.R. Hurson

21. An interrupt mechanism is a built-in facility
An interrupt mechanism is a built-in facility. It is a signal to the processor that causes the processor, after completing its current instruction, to fetch the next instruction from a special location in memory.
The occurrence of an interrupt allows the processor to finish what it is currently doing with its program and then simply leave that program and begin executing another one.
A.R. Hurson

22. The concept of program interrupt is used to handle a variety of problems which arise out of the normal program sequence.
Program interrupt refers to the transfer of control from the currently running program to another service program as a result of an external or internal generated request. Control might return to the original program after the service program is executed.
A.R. Hurson

23. Types of Interrupt
External Interrupt is initiated mainly by external devices, such as I/O devices, to the main frame.
Internal Interrupt is initiated as a result of executing an instruction.
Software Interrupt is initiated by executing an instruction. It is a special instruction call that behaves like an interrupt rather than a subroutine call. It can be initiated by the programmer at any time in the program.
A.R. Hurson

24. Internal Interrupt (Examples):
Arithmetic results out of range
Parity error
Illegal operation code
Stack overflow/underflow
Out of memory access
External Interrupt (Examples):
Input/output devices started earlier is finished
Another processor needs attention
Operator at console
A.R. Hurson

25. Register: It is a group of binary cells suitable for holding binary information (i.e., an array of flip- flops).
Bits in a register are numbered - either from left- to-right or right-to-left, starting either from 0 or 1.
Registers can be:
General purpose
Special purpose
Storage type
Operational type
A.R. Hurson

26. Graphically a register is represented by a rectangle:
A.R. Hurson

27. Wimp51 block diagram CU IR R0 R1 R2 ALU R3 ACC R4 R5 R6 R7 1 PC ALU
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in

28. Wimp51 block diagram includes:
Registers include the eight-bit
ACCumulator (ACC),
Instruction Register (IR),
Program Counter (PC),
AUXiliary register (AUX), and
R0-R7 registers;
Single-bit C and Z flags; and
Two-bit current state register inside the control unit.
A.R. Hurson

29. Wimp51 block diagram includes:
The logic includes;
AUX input multiplexor,
Control Unit to decode instruction, determines next state logic (CU), and
Two arithmetic and logic units (ALU and PCALU).
The data bus and address bus are connected to external memory. The address bus is driven by the Wimp51. When the active-low signal PSEN goes low, the external RAM, ROM, or I/O will drive the data bus with the data from the appropriate address.
A.R. Hurson

30. PC is an eight bit counter, 0 to 255
PC can also be loaded from the abus
ACC and ALU form a ‘register with logic’ block
IR and memory form a ‘register with logic’ block
Control Unit (CU) includes a 2 bit counter, 0 to 2
Datapath = IR, AUX, PC, ACC, Regfile, ALU, PCALU
12 registers plus Logic (ALU, PCALU)
A.R. Hurson

31. WIMP51 Control Unit Circuit includes:
00 = Fetch 01 = Decode 10 = Execute
A.R. Hurson

32. WIMP51 Instruction Set
INST BINARY HEX DESCRIPTION MOV A, #D dddddddd 74 dd A←D MOV A, Rn 11101nnn E8-EF A ← Rn MOV Rn, A 11111nnn F8-FF Rn ← A ADDC A, #D dddddddd 34 dd C,A ← A+D+C ADDC A, Rn 00111nnn 38-3F C,A ← A+Rn+C ORL A, Rn 01001nnn 48-4F A ← A OR Rn ANL A, Rn 01011nnn 58-5F A ← A AND Rn XRL A, Rn 01101nnn 68-6F A ← A XOR Rn SWAP A C4 A ← A(3-0)&A(7-4) CLR C C3 C ← 0 SETB C D3 C ← 1 SJMP rel aaaaaaaa 80 aa PC ← PC+rel+2 JZ rel aaaaaaaa 60 aa PC ← PC+rel+2 if A=0
The Wimp51 has a primary 8 bit opcode.
Opcodes 74h and 34h are used for load and add immediate instructions. The next eight bits of the instruction are used as an immediate operand so these are called immediate mode instructions.
Opcodes F8-FF are called register destination instructions since they use the lower three bits of the opcode to select a register to write the result into.
Opcodes 38-3F, 48-4F, 58-5F, 68-6F, and E8-EF are all register source instructions since the lower three bits of the opcode select a register to read the second operand from.
Opcodes C3, C4, and D3 all operate on a single register and do not require any operand at all. The two jump instructions, opcodes 80h and 60h, require a second byte to be fetched from memory and added to the program counter. This second byte is called the relative address.
As you can see, there are many different kinds of instructions in the Wimp51 instruction set. Even more complex is the actual 8051 instruction set with a few more addressing modes and 98 more instructions.

33. Introduction to Micro Controllers & Embedded System Design
Simple instruction cycle
Fetch/Decode/Execute sub-cycles
Each state may take one or several clock cycle(s)
Fetch
Decode
Execute
Each state lasts for one clock cycle. During the fetch state the current instruction is fetched from code memory and loaded into the instruction register. During the decode state the instruction is decoded and any required operands are fetched from memory or from the register file. During the execute state the instruction is executed. A result may be stored in a register or the accumulator updated. All three states constitute what is often called an instruction cycle.
A processor designer is interested in reducing the number of states and in how fast the state machine can be clocked since both determine the speed of the processor. It’s no good to have a very high clock rate if it takes a large number of states per instruction.
Questions:
1. Draw a timing diagram showing a clock, the current state, and next state for at least two instruction cycles.
2. Describe what needs to be done to implement the state machine controller in hardware
A.R. Hurson

34. Fetch Cycle Step 1: PC → AddressCU
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in

35. Fetch Cycle Step 2: Instruction read → IRCU
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in
RAM

36. Fetch Cycle Step 3: Update PCCU
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in
RAM

37. Decode Cycle CU IR ALU ACC RAM PC ALU AUX PC 1 Information from memory
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in
RAM

38. Immediate source (MOV A, #05h)
Decode Cycle
Immediate source (MOV A, #05h) CU
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in
RAM

39. Register source (MOV A, R5)
Decode Cycle
Register source (MOV A, R5) CU
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in
RAM

40. Execute Cycle MOV A, R5 CU ALU IR ACC PC PC ALU AUX RAM 1
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in
RAM

41. Execute Cycle SJPM LOOP
PSEN
ACC_OUT
Information from memory
ALU C Z
ALU_OP IR
Ir_we R0 R1 R2 R3 R4 R5 R6 R7
Register File
Reg_we
Reg_sel
ACC
ACC_we PC
PC ALU
PCALU_OP
PC_we
Address to Memory
AUX
Aux_we 1
reg_in
RAM

42. WIMP51 Example Walkthrough
What’s the first phase of the instruction cycle called?
Clock Cycle 1

43. What is the instruction doing that we are fetching?
Clock Cycle 1

44. 74h =
MOV A, #d
What is the next state in the instruction cycle?
What else needs to occur for this instruction to execute?
Clock Cycle 2

45. What is the final state in the instruction cycle?
Decode
Phase
03h =
MOV A, #d
What is the final state in the instruction cycle?
Clock Cycle 3

46. Execution Phase
Clock Cycle 4

47. F8h =
MOV R0, A
Clock Cycle 5

48. F8h =
MOV R0, A
Clock Cycle 6

49. F8h =
MOV R0, A
Clock Cycle 7

50. 74h =
MOV A, #d
Clock Cycle 8

51. 0Fh =
MOV A, #d
Clock Cycle 9

52. 0Fh =
MOV A, #d
Clock Cycle 10

53. F9h =
MOV R1, A
Clock Cycle 11

54. F9h =
MOV R1, A
Clock Cycle 14

55. 74h =
MOV A, #D
Clock Cycle 17

56. FAh =
MOV A, #D
Clock Cycle 20

57. Write the assembly code for the WIMP51 to calculate 2+1?

58. Write the assembly code for the WIMP51 to calculate 2+1?