1. Spring 2002 www.engr.wisc.edu/ece/courses/ece554.html
ECE 554 HW Tutorial
Spring 2002
Good afternoon everyone.
Welcome ECE 554 Digital Engineering laboratory.
In this fall 2000 semester, our web page is at
as shown here.

2. OBJECTIVES Hardware setup Configuration (.bit) download
Introduction to logic analyzer
To satisfy the previous motivations, ECE 554 is being offered with the following objectives.
To deal with problems and solutions associated a large digital system is a worthwhile experience for undergraduate students before going out to the industry.
To work effectively in a big group of 5-7 persons is another good opportunity.
To use current technology of FPGA for rapid prototyping is unavoiadble in the industry since it is used everywhere.
To learn how to use contemporary design tool gives you an edge in getting a better job.

3. Hardware setup Probe CLK pin and ground it properly
Turn on the equipment
Make sure that all the knobs on the pulse generator are at the “black” mark
Adjust the clock frequency and read it from the scope

4. Configuration Download
Parallel Cable
Serial Cable
NT machine running
GXSTools V.3.3
- GXSLoad
- GXSPort
Do you have any question so far ?
I guess so.
I hope it will become clear for you when you start working on the miniproject.
Up to this point, we’ve got a configuration bitstream implemented.
It’s time to download it to the FPGA.
This is done via a PC parallel or printer port.

5. Manuals GXSTools V.3.3 (Being used) GXSTools V.4.0 (Coming soon)
GXSLoad
GXSPort
GXSTools V.4.0 (Coming soon)

6. Logic Analyzer: Functionality
Timing Analyzer
State Analyzer

7. Timing Analyzer: How it works
Synchronizes with target CLK
Samples every 1/fs = 2n *4 ns, n=0,1,..
It has limited amount of storage
Samples with a transition detector
Set the right fs for your signals

8. Sampling at high resolution

9. Sampling with a transition detector

10. Triggering on events

11. State Analyzer: State Trigger

12. State Trigger

13. State Analyzer: Hex codes translated into assembly code

14. SRAM Loader Left Right 32-bit data 19-bit addr MSBs LSBs 512 k words
WEB
OEB

15. Logic Analyzer and XSV Board
Pod A[15:0]=Data[31:16]
Pod B[15:0]= Data[15:0]
Pod C[15:0]=Addr[15:0]
D[0]=CLK,D[1]=WEB,D[2]=OEB