1. Composing the Elements
First-cut data path does an instruction in one clock cycle
- Each datapath element can only do one function at a time
- Hence, we need separate instruction and data memories
Use multiplexers where alternate data sources are used for different instructions
August 2009
© McQuain, Feng & Ribbens

2. R-Type/Load/Store Datapath
How would this execute: add $s0, $s1, $s2;
100000
00000
10000
10010
10001
000000
funct
shamt rd rt rs op
August 2009
© McQuain, Feng & Ribbens

3. R-Type Execution
100000
00000
10000
00011
10001
000000
funct
shamt rd rt rs op
Reg #s for $s1 and $s2 are input to the register file's read register ports.
Values from $s1 and $s2 are fetched and passed to ALU (ALUSrc set to 0 by Control).
Low 16 bits from instruction are fed to the Sign-extend logic… irrelevant.
August 2009
© McQuain, Feng & Ribbens

4. R-Type Execution
100000
00000
10000
00011
10001
000000
funct
shamt rd rt rs op
ALU computes sum of operands (ALU operation control set by Control).
ALU output tranferred to MUX, set to pass through input 0 by Control.
August 2009
© McQuain, Feng & Ribbens

5. R-Type Execution
100000
00000
10000
00011
10001
000000
funct
shamt rd rt rs op
Reg# for $s0 is input to register file write register port.
ALU output transferred to register file Write data port.
RegWrite control line set by Control.
August 2009
© McQuain, Feng & Ribbens

6. R-Type/Load/Store Datapath
How would this execute: lw $s0, 16($s1);
10001
10000
100011
16-bit number rt rs op
QTP Alert!!
August 2009
© McQuain, Feng & Ribbens

7. Full Datapath How would this execute: beq $s0, $s1, Label0;
QTP Alert!!
August 2009
© McQuain, Feng & Ribbens

8. Simplified ALU Design
Here's a simplified ALU for 4-bit operands that illustrates the control interface we need:
Effectively, this ALU has a 4-bit control mechanism for selecting the desired function.
InvA
InvB
FnSel
ALU Fn 00
AND 01 OR 10
add 1
sub 11
slt
NOR
August 2009
© McQuain, Feng & Ribbens

9. ALU Control ALU used for - Load/Store F = add - Branch F = subtract
- R-type F depends on funct field
InvA
InvB
FnSel
ALU Fn 00
AND 01 OR 10
add 1
sub 11
slt
NOR
August 2009
© McQuain, Feng & Ribbens

10. ALU Control Assume 2-bit control signal ALUOp derived from opcode
- Combinational logic derives ALU control
opcode
ALUOp
Operation
funct
ALU function
ALU control lw 00
load word
XXXXXX
add
0010 sw
store word
beq 01
branch equal
subtract
0110
R-type 10
100000
100010
AND
100100
0000 OR
100101
0001
set-on-less-than
101010
0111
ALU
Control
August 2009
© McQuain, Feng & Ribbens

11. write for R-type and load
The Main Control Unit
Control signals derived from instruction
R-type rs rt rd
shamt
funct
31:26
5:0
25:21
20:16
15:11
10:6
write for R-type and load
Load/ Store
35 or 43 rs rt
address
31:26
25:21
20:16
15:0
sign-extend and add 4 rs rt
address
31:26
25:21
20:16
15:0
Branch
opcode
always read
read, except for load
August 2009
© McQuain, Feng & Ribbens

12. Datapath With Control CS@VT August 2009
© McQuain, Feng & Ribbens

13. Datapath Control Signals
RegDst selects instruction bits for write register #
Branch 1 iff instruction is beq
MemRead 1 iff memory location is to be read
MemtoReg selects source for write data port
ALUOp specifies instruction class to ALU control
MemWrite 1 iff memory location is to be written
ALUSrc selects source for 2nd operand to ALU
RegWrite 1 iff register is to be written
August 2009
© McQuain, Feng & Ribbens

14. Main Control Truth Table
The bottom portion of the table gives the outputs for each of the four opcodes.
If we consider only the four opcodes shown in this table, then we can simplify the truth table by using don’t cares in the input portion. For example, we can detect an R-format instruction with the expression Op5 || Op2, since this is sufficient to distinguish the R-format instructions from lw, sw, and beq. We do not take advantage of this simplification, since the rest of the MIPS opcodes are used in a full implementation.
August 2009
© McQuain, Feng & Ribbens

15. Relevancies for R-Type Instruction
August 2009
© McQuain, Feng & Ribbens

16. Relevancies for Load Instruction
August 2009
© McQuain, Feng & Ribbens

17. Relevancies for beq Instruction
August 2009
© McQuain, Feng & Ribbens

18. Implementing Jumps 2 address Jump Jump uses word address
31:26
25:0
Jump uses word address
Update PC with concatenation of
- Top 4 bits of old PC
- 26-bit jump address
- 00
Need an extra control signal decoded from opcode
August 2009
© McQuain, Feng & Ribbens

19. Datapath With Jumps Added
August 2009
© McQuain, Feng & Ribbens

20. Performance Issues Longest delay determines clock period
- Critical path: load instruction
- Instruction memory  register file  ALU  data memory  register file
Not feasible to vary period for different instructions
Violates design principle
- Making the common case fast
We will improve performance by pipelining
August 2009
© McQuain, Feng & Ribbens