1. IAS 0600 Digital Systems Design
Data types in VHDL
IAS 0600 Digital Systems Design
Alexander Sudnitson
Tallinn University of Technology

2. Data Types
A signal’s type determines the set of values it can take and the set of operations that can be performed on those values.
VHDL is a strongly typed language with strictly enforced type rules. If we mix different types in an expression or exceed a type’s range of values, the compiler or simulator generates an error message. For example, the integer value 0, the real number 0.0, and the bit value '0' are not the same type, and, therefore, are not the same. VHDL’s strong typing makes it easier for a compiler to detect errors.

3. STD_ULOGIC (enumeration type)
Type STD_ULOGIC is declared inpackage STD_LOGIC_1164 as:
type_ulogic is ('U‘, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);
Type STD_ULOGIC is unresolved type. By default, types whether predefined or user defined, are unresolved. It is illegal for two sources to drive the same signal (compiler error is generated).
Using STD_ULOGIC has an advantge that if our design unintenentionally creates two sourses for a signal (conflict), we can catch this error during compilation.

4. State and strength properties of std_ulogic
Value
Meaning
'U'
Uninitialized
‘X’
Forcing (Strong driven) Unknown
‘0’
Forcing (Strong driven) 0
‘1’
Forcing (Strong driven) 1
‘Z’
High Impedance
‘W’
Weak (Weakly driven) Unknown
‘L’
Weak (Weakly driven) 0. Models a pull down.
‘H’
Weak (Weakly driven) 1. Models a pull up.
‘-’
Don't Care

5. Syntax for signal, type, subtype declaration
Std_logic is a subtype of std_ulogic
subtype std_logic is resolved std_ulogic;
resolved is the name of a resolution function (see next slide)
A subtype declaration does not define a new type. The type of a subtype is the same as its base type. Accordingly, the set of operations allowed on a subtype is the same as the set allowed on its base type.

6. Resolution table for std_logic
resolved function
uninitialized
unknown
forcing low
forcing high
high impedance
weak low
weak high
Don’t Care
weak unknown

7. STD_LOGIC versus STD_ULOGIC
STD_LOGIC is a type declared with a resolution function (defines, for all possible combinations of one or more sorce values, the resulting (resolved) value of a signal).
Example: a circuit with three-state outputs used in a bus interface; this is a situation where we intend for a signal to have multiple sources.
Std_logic is a subtype of Std_ulogic (but both consist of the same nine values) and is declared in package STD_LOGIC_1164 (there is defined resolution function with the name resolved).

8. STD_LOGIC versus STD_ULOGIC
A disadvantage of using std_logic instead of std_ulogic is that signals that are unintententionally multiply driven will not be detected as an error during compilation.
However, Standard IEEE Std 1164 recomends that std_logic be used instead of std_ulogic, even if a signal has only a single sourse (vendors have to optimize the simulation of models using unresolved types in accordance with Standard).

9. Three state buffers
A three-state buffer is represented by a triangle symbol.
Some three-state buffers are enabled when their enable input is '0‘ and others when it is '1'.
A three-state buffer has a data input and an enable input. Its enable input controls whether the three-state buffer is OFF and its output is high impedance ('Z'), or whether it is ON and its output is driven by its data input. Thus, the output of a three-state buffer can be either '0', '1', or 'Z'.

10. Three state buffer description
library ieee;
use ieee.std_logic_1164.all;
entity three_state_buffer is
port (
d_in, en_bar : in std_logic;
d_out: out std_logic );
end three_state_buffer;
architecture dataflow of three_state_buffer is
begin
d_out <= d_in when en_bar = '0' else 'Z';
end dataflow;
If the enable input en_bar is asserted (low active), the buffer’s output is the same as its input. If the enable input is not asserted, the buffer’s output is 'Z'.

11. Multiplexing two data sources
If none of the buffers is enabled, both outputs are in their high impedance states and the shared signal they drive has the high impedance value.

12. Two buffers with their outputs connected
Here we assume that the three-state buffer entity has been compiled to the library three_state_buffer.
library ieee; use ieee.std_logic_1164.all;
library three_state_buffer; -- library containing buffer
use three_state_buffer.all;
entity three_state_bus is
port (
d_a: in std_logic; -- data input buffer a
en_a_bar: in std_logic; -- enable input buffer a
d_b: in std_logic; -- data input buffer b
en_b_bar: in std_logic; -- enable input buffer b
d_bus: out std_logic -- bused data output );
end three_state_bus;

13. Two buffers with their outputs connected
architecture three_state_bus of three_state_bus is
begin
u1: entity three_state_buffer port map (d_a, en_a_bar, d_bus);
u2: entity three_state_buffer port map (d_b, en_b_bar, d_bus);
end three_state_bus;
The direct component instantiation statement with positional association is used in this description.

14. Timing waveform
For the second input combination, indicated by the cursor, the output for this case is 'X', because one buffer is trying to drive the output to a '1' and the other is trying to drive it to a '0'. On the output waveform, the times during which the output is forcing an unknown value ('X') are represented by two lines.
For input conditions corresponding to one buffer enabled and the other not enabled, the output is the same as the enabled buffer’s input value. When both buffers are not enabled, the output is 'Z'. This value is represented on the waveform by a line halfway between the '0' and '1' logic levels.

15. STD_LOGIC_VECTOR type
wire a
bus b 1 8
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 downto 0);
type std_logic_vector is array (natural range <>) of std_logic;

16. Standard logic vectors
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= '1';
b <= "0000"; Binary base assumed by default
c <= B"0000"; Binary base explicitly specified
d <= "0110_0111"; -- You can use '_' to increase readability
e <= X"AF67"; Hexadecimal base
f <= O"723"; Octal base

17. Vectors and Concatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= "0000";
b <= "1111";
c <= a & b; c = " "
d <= '0' & " "; d <= " "
e <= '0' & '0' & '0' & '0' & '1' & '1' &
'1' & '1'; -- e <= " "

18. Single versus Double quote
Use single quote to hold a single bit signal
a <= '0', a <='Z‘
Use double quote to hold a multi-bit signal
b <= "00", b <= "11"

19. Aggregates
An aggregate combines one or more values to form a composite. This is one approach used to combine scalars into an array or to combine multiple buses into one.
Eample:
x <= ('1','0','1','1');
Positional association:
x(3) <= '1';
x(2) <= '0';
x(1) <= '1';
x(0) <= '1';
Named association:
x <= (3 =>'1', 1 => '1', 0 => '1', 2 => '0');

20. x <= (others => '0');
Aggregates
Eample (cont):
x <= ('1','0','1','1');
x <= (2 => '0', others => '1');
x <= (3|1|0 =>'1', 2 => '0');
If we wanted to make the value of all the elements in the vector equal to '0' we can simply write:
x <= (others => '0');

21. Our use of Std_logic values
We are interested in writing descriptions that will be synthesized and then implemented using FPGA (PLD).
In PLD/VHDL design methodology we will assign only the values ‘0’, ‘1’, or ‘–’ to std_logic signals. Sometimes we add ‘z’ to the previous list of values. Assigning values ‘H’ and ‘L’ to signals is not compatible with the device technology normally used in FPGAs (PLDs).
For testbenches we typically assign only the values ‘0’ and ‘1’ as inputs to the UUT.
During simulation we may observe the value ‘U’ and sometimes the value ‘X’. Since we will not assign values ‘H’ and ‘L’ to signals, we don’t expect to obseve the value ‘W’.

22. The predefined type bit
Type bit is an enumeration type used as a simple representation for a logic signal.
The type declaration for bit appears in package STANDARD as:
type bit is ('0','1');
Here character literals '0' and '1' are used to represent logic 0 and logic 1. Hence, type bit is also a character type. Because of their order in the enumeration list, '0’ is less than '1'.
Type bit_vector is a predefined one-dimensional unconstrained array of elements of type bit, defined in package STANDARD as:
type bit_vector is array ( natural range <> ) of bit;

23. The predefined type boolean
The predefined type boolean is defined as
type boolean is (false, true);
This type is used to represent condition values, which can control execution of a behavioral model. There are a number of operators that we can apply to values of different types to yield Boolean values, namely, the relational and logical operators. The relational operators equality (“=”) and inequality (“/=”) can be applied to operands of any type, provided both are of the same type.
For example, the expressions
123 = 123, 'A' = 'A', 7 ns = 7 ns
all yield the value true, and the expressions
123 = 456, 'A' = 'z', 7 ns = 2 us
yield the value false.

24. Types UNSIGNED and SIGNED
Type std_logic is not defined as a numeric representation, no arithmetic operators are not defined for it in package STD_LOGIC_1164.
To avoid confusion separate types werw created for numeric representation in package NUMERIC_STD:
type unsigned is array (natural range <>) of std_logic;
type signed is array (natural range <>) of std_logic;
Type signed is interpreted as a signed binary number in 2´s complement form. The leftmost element is the sign bit.

25. Context clause to use unsigned and signed
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

26. Type conflict
When a signal assignment is made, the objects on both sides of the assignment symbol must be of the same type. Otherwise, the compiler gives a type conflict error.
To make an assignment of the value of one type to one of the others, the type of the value being assigned must be converted to the target type.
For example, if signal x is declared as type std_logic_vector and signal y is declared as type unsigned, and they are of equal length, each of the following assignments is illegal:
x <= y ; --illegal assignment, type conflict
y <= x ; --illegal assignment, type conflict
However, appropriate type conversions allow the following assignments to be made:
x <= std_logic_vector (y) ; -- valid assignment
y <= unsigned (x) ; -- valid assignment

27. Conversion between Std_logic_vector, Unsigned and Signed
This conversion is easy to accomplish because these are considered closely related. Type conversion between closely related types is accomplished by simply using the name of target type as it were a function.
For example, if x is std_logic_vector and y is unsigned, and they are ofequal length, than asigments
x <= y; and y <= x;
are illegal.
Type conversions are allowed assignments to be made:
x <= std_logic_vector (y);
y <= unsigned (x);

28. Functions to convert between types signed and unsigned and integer
Examples:
y <= to_unsigned (i, 8);
(This function’s first parameter is the non-negative integer to be converted. Its second parameter is the number of elements in the unsigned vector it is being converted to)
x <= std_logic_vector (to_unsigned (i, 8));
(Assignment integer i to std_logic_vector signal x)

29. Type translations made by a synthesizer
A synthesizer must translate all types used for signals into types that can represent wires. Typically, a synthesizer converts all types to either std_logic or std_logic_vector.