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Published byBrett Henry Modified over 6 years ago
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Last time Analysis vs Design General tasks for analysis
General design strategies
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Analysis examples Simple current mirrors Common source Common drain
Common gate Cascoded CM Cascoded CS
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Today’s focus Large signal DC analysis Goal:
Which operation region is transistor in Write nonlinear ID vs terminal voltage eq Solve for Q point I and V Goal: Obtain constraints, V swing ranges Obtain Q point Design strategies
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NMOS CM Chapter 3 Figure 01
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PMOS CM Chapter 3 Figure 04
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CS: N-input, P-load Chapter 3 Figure 04
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Common drain, i.e., source follower N-input, P-load
Chapter 3 Figure 04 Chapter 3 Figure 06
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