1. Last time Analysis vs Design General tasks for analysis
General design strategies

2. Analysis examples Simple current mirrors Common source Common drain
Common gate
Cascoded CM
Cascoded CS

3. Today’s focus Large signal DC analysis Goal:
Which operation region is transistor in
Write nonlinear ID vs terminal voltage eq
Solve for Q point I and V
Goal:
Obtain constraints, V swing ranges
Obtain Q point
Design strategies

4. NMOS CM
Chapter 3 Figure 01

5. PMOS CM
Chapter 3 Figure 04

6. CS: N-input, P-load
Chapter 3 Figure 04

7. Common drain, i.e., source follower N-input, P-load
Chapter 3 Figure 04
Chapter 3 Figure 06