1. Lecture 33 Syed Mansoor Sarwar
Operating Systems
Lecture 33
Syed Mansoor Sarwar

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Agenda for Today
Review of previous lecture
Addressing and logical to physical address translation
Examples: Intel P4 and PDP-11
Page table implementation
Performance of paging
Protection in paging
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Review of Lecture 32
MVT
Paging
Addressing and address translation in paging
1 January 2019
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4. Paging Process Address Space Physical Address Space 1 2 1 2 … 3 4 5 61 2 … 9 10 15 1 2 3 4 5 6 7
Process Address Space
Physical Address Space
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5. Paging Process Address Space Physical Address Space Page Page Table 11 2 … 9 10 15 1 2 3 4 5 6 7
Page 3 9 11 … 1 1 2 3 … 7
Page Table
Process Address Space
Physical Address Space
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6. Paging Process Address Space Physical Address Space Page Table 1 2 3 …1 2 … 9 10 15 1 2 3 4 5 6 7 9 … 1 2 3 … 7
Page Table
Process Address Space
Physical Address Space
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Address Translation f
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Paging Example
Page size = 4 bytes
Process address space = 4 pages
Physical address space = 8 frames
Logical address: (1,3)
= 0111
Physical address: (6,3)
= 11011
Page
Frame 1
0111 2 3
11011
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Addressing in Paging
Logical address space of 16 pages of 1024 words each, mapped into a physical memory of 32 frames.
Logical address size?
Physical address size?
Number of bits for p, f, and d?
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Addressing in Paging
No. of bits for p = ceiling [log2 16] bits
= 4 bits
No. of bits for f = ceiling [log2 32] bits
= 5 bits
No. of bits for d = ceiling [log2 2048] bits
= 11 bits
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Addressing in Paging
Logical address size = |p| + |d|
= 4+11
= 15 bits
Physical address size = |f| + |d|
= 5+11
= 16 bits
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Page Table Size
Page table size = NP * PTES
where NP is the number of pages in the process address space and PTES is the page table entry size (equal to |f| based on our discussion so far).
Page table size = 16 * 5 bits
= 16 bytes
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Paging in Intel P4
32-bit linear address
4K page size
Maximum pages in a process address space = 232 / 4K
Number of bits for d = log2 4K = 12
Number of bits for p =
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Paging in PDP-11
16-bit logical address
8K page size
Maximum pages in a process address space = 216 / 8K = 8
|d| = log2 8K = 13 bits
|p| = 16 – 13 = 3 bits
|f| = ? bits
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Another Example
Logical address = 32-bit
Process address space = 232 B
= 4 GB
Main memory = RAM = 512 MB
Page size = 4K
Maximum pages in a process address space = 232 / 4K = 1M
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Another Example
|d| = log2 4K = 12 bits
|p| = 32 – 12 = 20 bits
No. of frames = 512 M / 4 K
= 128 K
|f| = ceiling [log2 128 K] bits
= 17 bits ≈ 4 bytes
Physical address = bits
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17. Implementation of Page Table
In CPU registers
OK for small process address spaces and large page sizes
Effective memory access time (Teffective) is about the same as memory access time (Tmem)
PDP-11
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18. Implementation of Page Table
Keep page table in the main memory
Page table base register (PTBR)
Teffective = 2Tmem
Teffective is not acceptable
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19. Implementation of Page Table
Use a special, small, fast lookup hardware, called translation look-aside buffer (TLB)
Typically 64–1024 entries
An entry is (key, value)
Parallel search for key; on a hit, value is returned
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20. Implementation of Page Table
(key,value) is (p,f) for paging
For a logical address, (p,d), TLB is searched for p. If an entry with a key p is found, we have a hit and f is used to form the physical address. Else, page table in the main memory is searched.
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TLB
Logical address: (p, d) f p
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22. Implementation of Page Table
The TLB is loaded with the (p,f) pair so that future references to p are found in the TLB, resulting in improved hit ratio.
On a context switch, the TLB is flushed and is loaded with values for the scheduled process.
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Paging Hardware
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Performance of Paging
Teffective on a hit = Tmem + TTLB
Teffective on a miss = 2Tmem + TTLB
If HR is hit ratio and MR is miss ratio, then
Teffective = HR (TTLB + Tmem)
+ MR (TTLB + 2Tmem)
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Example
Tmem = 100 nsec
TTLB = 20 nsec
Hit ratio is 80%
Teffective = ?
Teffective = 0.8 ( )
+ 0.2 (20 + 2x100)
= 140 nanoseconds
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Example
Tmem = 100 nsec
TTLB = 20 nsec
Hit ratio is 98%
Teffective = ?
Teffective = 0.98 ( )
(20 + 2x100)
= 122 nanoseconds
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Recap of Lecture
Logical and physical addresses
Address translation
Intel P4 example
PDP-11 example
Implementation of page table
Performance of paging
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Operating Systems
Lecture 33
Syed Mansoor Sarwar
1 January 2019
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