Systems Manufacturing Training and Employee Development

Systems Manufacturing Training and Employee Development
Chapter 10 Pentium™ Processor Fundamentals PC Architecture for Technicians: Level-1 Systems Manufacturing Training and Employee Development Copyright © 1996 Intel Corp.

Introduction The knowledge acquired here about the Pentium™ processor features, architecture, signals and key bus cycles will serve a foundation for the boards based on this processor. This overview will describe the features of the Pentium as used in a typical Single Processor PC system in Real Mode. Multiprocessor support signals and MESI protocol signals are beyond the scope of this course. Protected Mode Registers and related features are beyond the scope of this course.

OBJECTIVES: At the end of this section, the student will be able to do the following:
Describe the basic architecture of the Pentium processor. Explain the use of the Pentium Registers. Describe the various Pentium buses. Explain the use of the Byte Enables . Discuss Pentium address generation. Discuss Pentium Bus Cycle Definitions. Describe Pentium Single & Burst cycles. Discuss Pentium Signal Descriptions.

Intel Family Comparison

The Intel 86 Family of Processors
Year Internal Architecture External Bus Size Transistors Principle Features 86 1978 16 29K 16-bit architecture, basic segment protection 88 1979 8 Same as 86, but with 8-bit processor bus. (IBM PC) 286 1982 130K Expands segmentation protection, adds single- instruction task switching (used in IBM PC/AT) Intel 386TM 1985 32 375K Adds paging, 32-bit extensions, on-chip address translation, and greater speed to 286 functions SX 1988 Same as Intel 386 processor, but with a 16-bit data bus

The IntelTM 86 Family of Processors
Year Internal Architecture External Bus Size Transistors Principle Features Intel 486TM DX 1989 32 1,200K Adds on-chip cache, floating- point unit, and greater speed to Intel386TM 1991 Intel486TM SX No math, Lower cost The IntelTM 86 Family of Processors DX-2 1992 1.2 Meg Double internal speed PentiumTM P5 - 60,66 64 1993 3.1 Meg Superscaler, Code & Data Cache, 64 bit data bus P54C 1994 3.3 Meg 3.3v, Power Mgt, Multiprocessor support Pro 1995 CPU 5.5 Meg On Chip L1 & L2, Dynamic Execution GTL logic

Intel Family Comparison

THE iCOMP(TM) INDEX iCOMP
(Intel COmparative Microprocessor Performance). The iCOMP index is a simple numerical index of relative performance for making straightforward comparisons of Intel CPU power. The base processor for the iCOMP index is the 25-MHz Intel486TM SX processor, which has been assigned a value of 100. The size of the disparity between any two indices provides a relative measure of how much more powerful one CPU is than any other. It is an index that reflects the relative performance of one Intel microprocessor to another, not system performance.

Pentium™ Processor Architecture

Divide Add 64 bit bus Interface Code Cache Prefetch Buffers Integer ALU Register Set Data Cache Branch Prediction Pipelined Floating-Point Unit Multiply U pipe V pipeline 32 bits 64 bits 256 bits

The Pentium processors have a data bus of 64 bits. This is a 32 bit CPU due to having 32 bits registers. A standard Single Transfer Cycle can read or write up to 64 bits at a time (8 bytes) Burst read and burst write-back cycles are supported by the Pentium processors. Burst Mode cycles are used for Cache operations and transfer 32 bytes in 4 clocks (4 * 8 bytes = 4 * 64 bits). 32 bytes is the size of the Pentium Cache line. For the Pentium, all cache operations are burst cycles.

Divide Add 64 bit bus Interface Prefetch Buffers Code Cache Integer ALU Register Set Data Cache Branch Prediction Pipelined Floating-Point Unit Multiply U pipeline V pipeline Separate Code and Data caches On chip 8KB code and 8KB write back data cache. Two way set associative. MESI Cache protocol 32 bits 64 bits 256 bits

Pentium processors include separate Code and Data Caches which can be enabled or disabled by software or hardware. Each cache is 8-Kbytes in size, with a 32-byte line size and is 2-way set associative (4K/way). The Data Cache is configurable to be write-back or write-through on a line-by-line basis and follows MESI protocol. The Instruction Cache is an inherently write-protected cache (read-only)

Technical Innovations... Branch prediction: Processor makes predictions on next instruction to be executed via the BTB. Code Cache Branch Prediction 32 bits 64 bits 256 bits Prefetch Buffers Superscalar Architecture more than one execution unit U pipeline V pipeline Pipelined Floating-Point Unit 64 bit bus Interface Integer ALU Integer ALU NOTE: The Instruction Decode Unit is in the Prefetch Buffers on this diagram. Multiply Pipeline sequence Prefetch Decode1 Decode2 Execute Write Back Hardwired Instructions Register Set Add Divide Data Cache

Instructions are Fetched from the code cache or from the external bus. The decode unit Decodes the prefetched instructions so the Pentium processor can execute the instruction. Branch prediction is implemented with 2 Prefetch Buffers and a Branch Target Buffer so the needed code is almost always prefetched before it is needed for execution. Instructions are executed in 1 of 2 pipelines (“u” & “v” pipes) which share access to a single set of registers. No additional instructions can begin execution until both execution units complete their operations.

Pentium processors have two instruction pipelines. The u-pipe can Execute all integer and floating point instructions. The v-pipe can Execute simple integer instructions and the FXCH floating-point instructions. Pairing instructions in these two pipes enables the Pentium to operate on 2 instructions at the same time (Superscaler execution). The Control ROM unit has direct control over both pipelines. The Control ROM contains microcode which controls the sequence of operations that must be performed.

Pentium™ Processor Registers

Pentium Registers AH DH CH BH AL DL CL BL
7 15 23 31 16-BIT 32-BIT AX DX CX BX EAX EDX ECX EBX EBP ESI EDI ESP Segment Registers General Registers 16 8 CS SS DS ES FS GS AH DH CH BH AL DL CL BL EFLAGS EIP Status and Control NOTE: All registers in REAL MODE DEFAULT to 16 bits wide.

Segmented Addressing Code Segment Stack Data CS DS SS ES FS GS

Segmented Addressing NOTE: We will assume, unless otherwise stated, that all examples reflect real mode. Operand 15 Segment Register e.g - CS 15 Offset within segment e.g - IP

Pentium Registers (EFlags)
The EFlags register is not a normal register but a collection of FLAG BITS which indicate the result of previous operations or the current state of the CPU. A FLAG is just a flip-flop in the CPU that is SET (1) or RESET (0) [cleared] depending on the condition produced by an instruction . Some Flags indicate the condition produced by the previous instruction. e.g - Zero Flag: ZF=1 (True) if the result of the last arithmetic or logical operation was Zero. Some Flags are used to control certain operations. e.g. - IF (Interrupts Enabled); Trap Flag; Direction Flag.

Pentium Registers (EFlags)
ID X ID Flag (CPUID support) VIP X Virtual Interrupt Pending VIF X Virtual Interrupt Flag AC X Alignment Check VM X Virtual 8086 Mode RF X Resume Flag NT X Nested Task IOPL X I/O Privilege Level OF S Overflow Flag DF C Direction Flag IF X Interrupt Enable Flag TF X Trap Flag SF S Sign Flag ZF S Zero Flag AF S Auxiliary Carry Flag PF S Parity Flag CF S Carry Flag S = Status Flag C = Control Flag X = System Flag Bit Positions shown as “0” or “1” are Intel reserved. 31 ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF 23 1 15 7 CF

Pentium Registers (Debug)
BT BS BD GD DR3 - Breakpoint 3 Linear Address DR2 - Breakpoint 2 Linear Address DR1 - Breakpoint 1 Linear Address DR0 - Breakpoint 0 Linear Address LEN 3 R/W 2 1 GE LE G3 L3 G2 L2 G1 L1 G0 L0 0 0 1 0 0 Reserved

Pentium Registers (Debug)
The Debug Registers provide hardware support for setting breakpoints. You can define up to four breakpoints using Debug Registers (DR0 - DR3). The Debug Registers store the Linear Address. The linear address is the address after the addition of the Segment Base & the Offset (w/o Paging). This is the Physical Address in REAL MODE. When the Pentium address matches an address in one of the Debug Registers, the Pentium issues a Debug Exception (INT 1). This feature is used with the ITP Debug Tool.

Pentium™ Bus Description

Bus Description D63:0 Pentium™ Processor 64 bit Memory A31:3, BE7#:0#
Pentium™ Processor with 64 Bit Wide Memory Pentium™ Processor 64 bit Memory D63:0 A31:3, BE7#:0#

Bus Description Data Types Each location in memory is Byte wide Word
Low Byte High Low Word High Word Low Doubleword High Doubleword 7 15 31 Address N Address N+1 N Address N+1 Address N+2 Address N+3 47 63 Word Doubleword Address N+4 Address N+5 Address N+6 Address N+7 Data Types Each location in memory is Byte wide Quadword “Chunk”

Bus Description Physical Memory Space 64-BIT Wide Memory Organization
FFFFFFF8H FFFFFFFFH H H PHYSICAL MEMORY 4GB Physical Memory Space BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# 64-BIT Wide Memory Organization

CPU Bus Description I/O Space
I/O Address Space is limited to 64 Kbytes (0000H-FFFFH). This limit is imposed by a 16 bit CPU Register. A 16 bit register can store up to FFFFH ( y). Which CPU Register limits I/O space to 64K? H H I/O Space 64 KByte Not Accessible 0000FFFCH 0000FFFFH

CPU Bus Description Address bus: The microprocessor provides an address to the memory & I/O chips. The number of address lines determines the amount of memory supported by the processor. A31:A3 Address bus lines (output except for cache snooping) determines where in the 4GB memory space or 64K I/O space the processor is accessing.

CPU Bus Description The Pentium address consists of two sets of signals: Address Bus (A31:3) Byte Enables (BE7#:0#) Since address lines A2:0 do not exist on the Pentium, the CPU uses A31:3 to identify a group of 8 locations known as a Quadword (8 bytes -- also know as a “chunk”). Without A2:0, the CPU is only capable of outputting every 8th address. (e.g. 00H, 08H, 10H, 18H, 20H, 28H, etc.) A2:0 could address from 000 to 111 in binary (0-7H) 3 = = 111 2 = = 110 1 = = 101 0 = = 100

Example Addresses Output by CPU
Output on CPU Address Lines for addresses within a Quadword Addresses F Addr to be Output (in Hex) Addr Placed on CPU Addr Bus a b c d e f

CPU Bus Description The Pentium uses Byte Enables to address locations within a QWORD. BE7#:BEO# (outputs): Byte enable lines - to enable each of the 8 bytes in the 64-bit data path. In effect a decode of the address lines A2-A0 which the Pentium does not generate. Which lines go active depends on the address, and whether a byte, word, double word or quad word is required.

Relationship of Byte Enables to Locations Addressed within a QWORD

Pentium Processor Addressing Examples
Relationship of Addresses, Byte Enables, and locations accessed. (BE0#) 1 word starting at FE (BE7# & BE6#) 8 bytes starting at (BE7# through BE0#) 1 word starting at 0A5D0F0D (BE6# & BE5#) Addr A31:3 FE025600 0A5D0F08 Locations Addressed FE025606, FE025607 F 0A5D0F0D, 0A5D0F0E BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# 1 7 F 6 E 5 D 4 C 3 B 2 A 9 8

Pentium Processor Addressing Examples
Example Assembly Language Instructions and the resultant Addresses & Byte Enables. (Assume DS=0) MOV AL, [0100] (BE0#) MOV BH, [0105] (BE5#) MOV AX, [0104] - 1 word starting at (BE4# & BE5#) MOV EAX, [0100] -1 dword starting at (BE0# through BE3#) B E 7 # 6 5 4 3 2 1 Instruction MOV AL, [0100] MOV BH, [0105] MOV AX, [0104] MOV EAX, [0100] Addr on A31:3 Locations Addressed BIT BIT , BIT TO BITS

CPU Bus Description Data bus: The data bus provides a path for data to flow. The data can flow to/from the microprocessor during a memory or I/O operation. D63:DO (bi-directional): The 64-bit data path to or from the processor. The signal W/R# distinguishes direction. Control bus: The control bus is used by the CPU to tell the memory and I/O chips what the CPU is doing. Typical control bus signals are these: ADS# (output): Signals that the processor is beginning a bus cycle: BRDY# (input): This signal ends the current bus cycle and is used to extend bus cycles. (Ready Logic next page)

Ready Logic State Machine Example
TW= Time Wait

CPU Bus Description Control bus:(Cont.)
Typical control bus signals are these: (Cont.) M/IO# (output): Defines if the bus cycle is a Memory access or an Input/Output Port access. D/C# (output): Defines if the bus cycles is Data or Code for Memory access. W/R# (output): Indicates if bus cycle is a Write or a Read operation. Cache#. (output): Processor indication of internal cacheability. Cache# and Ken# are used together to determine of a read will be turned into a linefill. (Burst cycle).

Pentium™ Bus Cycles

Bus Cycles Definition M/IO# D/C# W/R# Cache# Ken# Cycle Description
No. of Transfers 1 x Interrupt Acknowledge (2 locked cycles) 1 transfer each cycle Special Cycle I/O Read , 32-bits or less Non Cacheable I/O Write , 32-bits or less Code Read, 64-bits, Code Read , 256-bit burst Line Fill 4 Intel Reserved (will not be driven by the Pentium™ processor). n/a Memory Read, 64 bit or less, Memory Read, 256 bit burst Memory Write, 64 bit or less 256 bit Burst Write back *Cache# will not be asserted for any cycle in which M/IO# is driven low, or for any cycle in which PCD is driven high.

GENERIC DECODE LOGIC The system board contain some logic to decode the BUS CYCLE DEFINITIONS of the CPU. The BUS CYCLE DEFINITIONS from the CPU are VALID when ADS# is asserted (Logic 0). The drawing shows an example of logic that could be used to decode the BUS CYCLE DEFINITIONS. The signals generated by the GENERIC DECODE LOGIC would be used by the System Board to generate signals such as I/O chip selects and DRAM & PROM output enables.

GENERIC DECODE LOGIC e.g. I/O WR @ Addr 43H 43H = 0100 0011y IOW M/IO#
D/C# W/R# INTA IOR IOW FETCH MEMR MEMW 486 / P5 SPECIAL INVALID D Q ADS# 1 e.g. I/O Addr 43H 43H = y

GENERIC DECODE LOGIC e.g. I/O WR @ Addr 43H 43H = 0100 0011y IOR IOW
( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) DMA #1 PIC #1 PIT Digital I/O - Kbd DMA Page PIC #2 DMA #2 FPU IOR IOW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 e.g. I/O Addr 43H 43H = y

Special Cycles Definition
M/IO# = 0, D/C# = 0, W/R# = 1 BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# Special Bus Cycle 1 Shutdown Flush (INVD, WINVD instr.) Halt Writeback (WBINVD Instruction) Flush Acknowledge (FLUSH# assertion) Brach Trace Message

Special Cycles Definition
Halt Cycle: CPU waits for INTR, NMI, Reset, or INIT. Generated when Pentium executes a HLT instruction. If interrupts are enabled, an INTR (e.g Timer Tick) will force the microprocessor out of a halt. Shutdown Cycle: CPU waits for NMI, Reset, or INIT. Generated by the Pentium: Triple Fault: The CPU detects a further exception (e.g. General Protection Fault, Invalid Op Code, Stack Overflow) while executing the Double Fault Exception handler. Internal Parity Error detected by the CPU. Shutdown is decoded by the system board and generates a soft reset (INIT to Pentium) in a PC.

CPU Bus Cycles A BUS CYCLE begins with the Processor driving an address and status (Control signals) and asserting ADS#. A BUS CYCLE ends when the last BRDY# is returned to the Processor. A BUS CYCLE may have 1 or 4 data transfers. A SINGLE Cycle transfer is 64 bits maximum [8 bytes]. The shortest cycle is 2 clocks A BURST Cycle transfer is 256 bits (4*64) [32 bytes]

Microprocessor Single Bus Cycle
ADDR CLK CACHE# BRDY# A31-A3 W/R# Byte Enables BE7:0# T1 T2 Ti D63-D0 ADS# READ MEMORY WRITE & READ WITH WAIT STATES WRITE WAIT STATE TO CPU FROM CPU IDLE DATA

Basic Burst Read Cycle READ ADDR CLK KEN# BRDY# A31-A3 BE7:0# W/R# T1
DATA A31-A3 BE7:0# W/R# T1 T2 Ti D63-D0 ADS# READ CACHE# CYCLE 1 2 3 4 TO CPU IDLE STATE

Basic Burst Cycle Burst Cycles can transfer larger quantities of data in fewer clocks than single transfer cycles. e.g. - Single Cycle: 8 bytes (64 bits) in 2 clocks. 4 Singles cycles = 32 bytes in 8 clocks. e.g. - Burst Cycle: 32 bytes (4*64 bits) in 5 clocks. The Pentium uses burst mode for: Cacheable read cycles Write-back cycles when writing back a cache line. Burst cycles are limited to an address area that begins at a 32-byte limit and the system board must calculate the other 3 burst addresses.

Basic Burst Cycle The system board must generate the subsequent addresses(2nd, 3rd, 4th) in the following sequence. Address Output by Pentium 1st 2nd 3rd 4th 00H 08H 10H 18H 08H 00H 18H 10H 10H 18H 00H 08H 18H 10H 08H 00H This is required in order to fill the Pentium 32t (20H) byte cache on 32 byte boundaries. e.g. 32 bytes for addresses 100H - 11FH 100H, 108H, 110H, 118H; or 110H, 118H, 100H, 108H, etc

Basic Burst Cycle These addresses can be generated as follows:
A3 toggles for every address; A4 toggles every OTHER address A A0 Address Output by Pentium H 08H 10H 18H H 00H 18H 10H

Pentium™ Signal Description

Pentium™ Signal Description
This overview will describe the signals of the Pentium as used in a typical Single Processor PC system. Multiprocessor support signals and MESI protocol signals are beyond the scope of this course.

Signal Description Pentium™ See the Pentium Data Book
Clock Probe Mode Initialization TAP Port Address Bus SMM Address Mask FP Error Reporting Internal Parity Error Interrupts Address Parity Pentium™ Bus Arbitration Data Bus Cache Flush Data Parity Cache Snooping Bus Cycles Definition Cache Control Bus Control See the Pentium Data Book Hardware Interface section for a complete description of all signals.

Signal Description CLOCK CLK - Clock (Input)
Fundamental Timing for the Pentium The CPU uses this signal as the internal processor clock. BF - Bus Frequency (Input) Bus Frequency determines the bus-to-core frequency ratio When BF is strapped to Vcc, the processor will operate at a 2 to 3 bus to core frequency ratio. When BF is strapped to Vss, the processor will operate at a 1 to 2 bus to core frequency ratio. What symptoms might be exhibited if this signal is incorrect?

Signal Description Initialization RESET - (Input)
Forces the CPU to begin execution at a known state. INIT - Initialization (Input) The Pentium processor initialization input pin forces the Pentium processor to begin execution in a known state. The processor state after INIT is the same as the state after RESET except that the internal caches, write buffers, and floating point registers retain the values they had prior to INIT.

Signal Description Address Bus A31:A3 - ADDRESS bus lines
Output except for cache snooping The number of address lines determines the amount of memory supported by the processor. Determines where in the 4GB memory space or 64K IO space the processor is accessing. These are input lines when AHOLD & EADS# are active for Inquire Cycles (snooping)

Signal Description Address Bus BE7#:BEO#: Byte Enable lines (Outputs)
Byte Enables to enable each of the 8 bytes in the 64-bit data path. Helps define the physical area of memory or I/O accessed. The Pentium uses Byte Enables to address locations within a QWORD. In effect a decode of the address lines A2-A0 which the Pentium does not generate. Which lines go active depends on the address, and whether a byte, word, double word or quad word is required.

Signal Description Address Mask Internal Parity
A20M#: Address 20 Mask (Input) Emulates the address wraparound at 1 MByte which occurs on the 8086. When A20M# is asserted, the Pentium processor masks physical address bit 20 (A20) before performing a lookup to the internal caches or driving a memory cycle on the bus. A20#M must be asserted only when the processor is in real mode. Internal Parity IERR# - Internal Error (Output) Alerts System of Internal Parity Errors

Signal Description Address Parity AP Address Parity (I/O)
Bi-directional address parity pin for the address lines. Address Parity is driven by the Pentium processor with even parity information on all CPU generated cycles in the same clock that the address is driven Even parity must be driven back to the CPU during inquire cycles on this pin in the same clock as EADS#. Not supported on all systems APCHK#: Address Parity Check Signal (Output) The status of the address parity check is driven on the APCHK# output. Even Parity Checking

Signal Description Data Bus. D63:DO - Data Lines (I/O).
The bi-directional 64-bit data path to or from the CPU. The signal W/R# distinguishes direction. During reads, the CPU samples the data bus when BRDY# is asserted. DP7: DP0 - Data Parity (I/O) Bi-directional data parity pins for the data bus. Even Parity Check. One for each byte of the data bus Output on writes, Input on reads. Not supported on all systems.

Signal Description Bus Control ADS# - Address Strobe (output)
Indicates that a new valid bus cycle is currently being driven by the Pentium processor. The following are some of the signals which are valid when ADS#=0 Addresses (A31:3) Byte Enables (BE7#:0#) Bus Cycle definition (M/IO#; D/C#; W/R#, CACHE#) From power-on the ADS# signal should be asserted periodically when bus cycles are running.

Signal Description Bus Control (Cont.) BRDY# - Burst Ready (Input)
Transfer complete indication. The burst ready input indicates that the external system has presented data on the data pins in response to a read or that the external system has accepted the Pentium processor data in response to a write request. This signal ends the current bus cycle and is used to extend bus cycles to allow slow devices extra time. If LOW (non-burst cycles), this signal ends the current bus cycle and the next bus cycle can begin. If HIGH the Pentium is prevented from continuing processing and wait states are added.

Signal Description Bus Cycle Definition
M/IO# - Memory or Input/Output (output) M/IO# distinguishes between Memory and I/O cycles. The memory/input-output is one of the primary bus cycle definition pins. 1 = Memory Cycle 0 = Input/Output Cycle It is driven valid in the same clock as the ADS# signal is asserted.

Signal Description Bus Cycle Definition (Cont.)
D/C# - Data or Code (output) D/C# distinguishes between data and code or special cycles (control) The data/code output is one of the primary bus cycle definition pins. 1 = Data 0 = Code / Control Control for Interrupt Acknowledge or Special Cycles It is driven valid in the same clock as the ADS# signal is asserted.

W/R# - Write or Read (output) W/R# distinguishes between Write and Read cycles. Write/read is one of the primary bus cycle definition pins. 1 = Write 0 = Read It is driven valid in the same clock as the ADS# signal is asserted.

Cache# - Cacheability (output) Processor indication of internal cacheability. The L1 cache must be enabled using the CD bit in CR0 for Cache# to be asserted low. The Cache# signal could also be described as the BURST instruction signal, because the Cache# signal (qualified with KEN#) results in a burst mode transfer of 32 bytes of code or data. Cache# and Ken# are used together to determine if a read will be turned into a linefill. (Burst cycle). During write-back cycles, the CPU asserts the CACHE# signal (KEN# does not have to be asserted)

NA# - Next Address (Input) Indicates external memory is prepared for a pipeline cycle. An active next address input indicates that the external memory system is ready to accept a new bus cycle although all data transfers for the current cycle have not yet completed. When NA# is asserted, the Pentium supplies the address for the start of the next transfer early, so that the memory system can latch the new address before the transfer is ready to start. A detailed discussion of Address Pipelining is beyond the scope of this course.

Lock# - Bus Lock (Output) The bus lock pin indicates that the current bus cycle is locked, typically for a read-modify-write operation. The CPU will not allow a bus hold when LOCK# is asserted. Locked cycles are generated when the programmer prefixes certain instructions with the LOCK prefix. e.g. LOCK INC [EDI] ;Increment a memory location Locked cycles are generated automatically for certain bus transfer operations. Interrupt Acknowledge cycles The XCHG instructions when 1 operand is memory-based. See Pentium manual for more details.

Signal Description Cache Control KEN# - Cache Enable (Input)
Indicates to the Pentium whether or not the system can support a cache line fill for the current cycle. Cache# and Ken# are used together to determine if a read will be turned into a linefill. (Burst cycle). WB/WT# - Write-back/Write-through (Input) This pin allows a cache line to be defined as a a write back or write-through on a line by line basis. This signal is necessary for the implementation of the MESI protocol. Detailed discussion of the MESI protocol is beyond the scope of this course.

Signal Description Cache Snooping AHOLD - Address Hold (Input)
Floats the address bus so an inquire cycle can be driven to the Pentium. AHOLD allows another bus master (e.g. DMA ctlr) to drive the CPU address bus with the address for an inquire cycle. Effectively changes address lines to inputs. All other signals remain active so data for previously sent bus cycles can still be transferred. EADS# - External Address Strobe (Input) Indicates that a valid external address has been driven onto the CPU address pins for a snoop inquire cycle. Recognized while AHOLD is asserted.

Signal Description Cache Snooping (Cont.)
HIT# - On Chip Cache hit (Output) Inquire Cycle Hit/Miss Indication Externally indicates whether an inquire cycle resulted in a hit or miss. HITM# - On Chip Cache Hit Modified (Output) Hit/Miss to a modified line Externally indicates whether an inquire cycle hit a modified line in the data cache. HITM# is never asserted without HIT# also being asserted

Signal Description Cache Flush Flush# - Cache Flush (Input)
Writes all modified lines in the data cache back and flushes the code and data caches. A Flush Acknowledge special cycle will be generated by the Pentium™ indicating completion of the invalidation and writeback.

Signal Description Bus Arbitration HOLD - Bus Hold (Input)
Allows another bus master complete control of the CPU bus. In response to the bus hold request, the Pentium processor will float most of its output and input/output pins and assert HLDA after completing all outstanding bus cycles. The Pentium processor will maintain its bus in this state until HOLD is de-asserted. HLDA - Bus Hold Acknowledge (Output) External indication that the Pentium™ outputs are floated.

Signal Description Bus Arbitration (Cont.) BOFF# - Backoff (Input)
Forces the Pentium to get off the bus in the next clock. After BOFF# is removed, the Pentium restarts the bus cycle. BREQ - Bus Request (output) Indicates externally when a bus cycle is pending internally. Used to inform the arbitration logic that the Pentium need control of the bus to perform a bus cycle.

Signal Description Interrupts INTR - Maskable Interrupt (Input)
Indicates that an external interrupt has been generated. If the IF(Interrupt Enable Flag) bit in the EFLAGS register is set, the Pentium processor will generate two locked interrupt acknowledge bus cycles (to get type number) and vectors to an interrupt handler after the current instruction execution is completed. NMI - Non-Maskable Interrupt (Input) Indicates that an external non maskable interrupt has been generated. The Pentium processor will vector to a Type 2 interrupt handler after the current instruction execution is completed.

Signal Description Floating Point Error Reporting
FERR# - Floating Point Error (Output) FERR# is included for compatibility with systems using DOS-type floating point error reporting (IRQ13) Indicates that an unmasked error occurred FERR# is similar to the ERROR# pin on the Intel387TM math coprocessor. IGNNE# - Ignore Numeric Exception (Input) Indicates ignore numeric exception. Valid only when CR0 NE bit is reset. Permits processor to continue execution before the floating point interrupt service routine has cleared the error.

Signal Description System Management Mode
SMI# - System Management Mode Interrupt (Input) Latches a System Management Interrupt Request When the latched SMI# is recognized on an instruction boundary, the processor enters System Management Mode SMIACT# - Sys Mgt Interrupt Active (Output) Indicates that the processor is operating in SMM.

Signal Description Test Access Port (TAP)
Signals for Hardware Debug Support (ITP) & Boundary Scan Testing. TCK - Testability Clock Input (Input) The testability clock input provides the clocking function for the Pentium processor boundary scan in accordance with the IEEE Boundary Scan interface. TMS - Test Mode Select (Input) The value of the test mode select input signal sampled at the rising edge of TCK controls the sequence of TAP controller state changes.

Signal Description Test Access Port (TAP) (Cont.)
TDI - Test Data Input (Input) The test data input is a serial input for the test logic. TAP instructions and data are shifted into the Pentium processor on the TDI pin on the rising edge of TCK when the TAP controller is in an appropriate state. TDO - Test Data Output (Output) The test data output is a serial output of the test logic. TAP instructions and data are shifted out of the Pentium processor on the TDO pin on TCK’s falling edge when the TAP controller is in the appropriate state.

Signal Description Test Access Port (TAP) (Cont.) Probe Mode
TRST# - Test Reset (Input) When asserted, the test reset input allows the TAP controller to be asynchronously initialized Probe Mode R/S# - Resume/Stop [Run/Scan] (Input) The run/stop input is an asynchronous, edge-sensitive interrupt used to stop the normal execution of the processor and place it into an idle state. PRDY - Probe Ready (Output) The probe ready output pin indicates that the processor has stopped normal execution in response to the R/S# pin going active. The CPU enters Probe Mode.

Pentium™ Address/Data Bus Exercise

Pentium Address/Data Bus Exercise
Assume you used an ITP debug tool to write the following into memory. Write 55H to 8 0:0 (0H-7H Physical) Write AAH to 8 0:8 (8H-0FH Physical) NOTE: Or vice versa (Address not significant) Result after reading the memory written to above! 0x P d 'UUUUU]UU' 0x P aa aa aa aa aa ba aa aa ' ' Using your knowledge of Pentium address & byte enable generation, determine what Data Bus problem could cause the bad data? Hint: D D0 d

Where to get more information
Pentium™ Processor User’s Manual Order Number Pentium™ Architecture & Programming Manual Order Number Pentium™ Processor System Architecture Mindshare (ISBN ) The Indispensable Pentium™ Book Addison-Wesley (ISBN )

WE HAVE DISCUSSED THE FOLLOWING:
SUMMARY WE HAVE DISCUSSED THE FOLLOWING: The basic architecture of the Pentium processor. The use of the Pentium Registers. The various Pentium buses. The use of the Byte Enables . Pentium address generation. Pentium Bus Cycle Definitions. Pentium Single & Burst cycles. Pentium Signal Descriptions.

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