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Computer System Design Lecture 5

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Presentation on theme: "Computer System Design Lecture 5"— Presentation transcript:

1 241-440 Computer System Design Lecture 5
Wannarat Suntiamorntut W.S.

2 Part II: Control Path for (Single Cycle)
W.S.

3 Outline Control for Register-Register Or Immediate Instructions
Control Signal for Load/Store Branch Jump Local control : ALU control Main control W.S.

4 Single Cycle Datapath W.S.

5 Add Instruction Add rd, rs, rt - Mem[PC] - R[rd] <= R[rs] + R[rt]
- PC = PC + 4 W.S.

6 Fetch Unit : Add W.S.

7 Single Cycle Datapath : Add
W.S.

8 Fetch Unit : End of Add W.S.

9 Single Cycle Datapath : Immed.
W.S.

10 Single Cycle Datapath : Immed.
W.S.

11 Single Cycle Datapath : Load
W.S.

12 Single Cycle Datapath : Store
W.S.

13 Single Cycle Datapath : Branch
W.S.

14 End of Branch instruction
W.S.

15 Summary of Control Signal
W.S.

16 Table of summary control signal
W.S.

17 Concept of Logical Control
W.S.

18 Decode of “func” Field W.S.

19 W.S.

20 Truth Table for Main Control
W.S.

21 Put It Together W.S.

22 Worst Case timing Load W.S.

23 Next on Lecture 6 W.S.


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