1. New PSB beam control rf clock distribution
PS TFB
New PSB beam control rf clock distribution
Required clock signal for the FMC “4ch ADC” and “4ch DAC”
Clock harmonic can change within cycle
Required clock signal for the transverse feedback and tune measurement
Fixed clock harmonic
No tag is required here but can be left as an option
see presentation on Clock requirements for precise timing specs
A. Blas
PSB Beam Control /05/2010

2. New PSB beam control rf clock distribution
PS TFB
New PSB beam control rf clock distribution
FMC 2ch DDS
Replaces the previous MDDS
The tag is created on the motherboard
The front panel has:
2 “ok” leds, one for each channel
2 e-sata connectors, one for each divided clock output
This a baseline architecture; some changes may show-up as being necessary during the design stage
A. Blas
PSB Beam Control /05/2010

3. New PSB beam control Memory requirements for the daughter cards
PS TFB
New PSB beam control Memory requirements for the daughter cards
What are the requirements for signal monitoring purposes ?
We would like to see up to four 16 bit traces during a specified time interval.
What sampling; what duration?
A full 1.2 s cycle recorded at 80 MHz means 100 M words of 16 bits for each trace.
This value is too high in our context to be asked for.
Some monitored signal are rf and typically will require the maximum sampling rate = rf clock.
They are usually observed during the occurrence of glitches. These glitches might occurs with some jitter in time but observing them within a 5 ms window is likely to be sufficient (=> 400 ks per trace at 80 MHz) and would also allow to make an FFT down to 200 Hz.
For down-mixed signals, observing a couple a synchrotron periods (50 or so) is likely to be sufficient. With a sampling rate around 10*FS, this means 500 samples per trace.
For monitoring purposes, a practical compromise =
memory with 500 k words of 16 bits for each FMC mezzanine; 120 Ms/s
A. Blas
PSB Beam Control /05/2010

4. New PSB beam control Memory requirements for the daughter cards
PS TFB
New PSB beam control Memory requirements for the daughter cards
What are the requirements for a record of a modulation signal?
We need to modulate the rf of 4 different channels during an entire accelerating cycle.
1st remark: the spectrum of the modulation will be within Fs and say 8 Fs. Whatever the modulating signal (sine wave or noise), it can cycle after one or a few synchrotron periods (say 10).
For aliases we need a sampling rate > 2 cavity BW; 1 Ms/s is sufficient in the PSB.
In the PSB, Fs>250 Hz (value at 2 GeV) => required number of samples >
1 Ms/s*10/250 = 40 ks /channel.
For modulation purposes, a practical value for the memory is:
200 k words of 16 bits for each FMC mezzanine; 10Ms/s
A. Blas
PSB Beam Control /05/2010

5. New PSB beam control Processing power for the daughter cards
PS TFB
New PSB beam control Processing power for the daughter cards
The Digital Down Conversion (most demanding circuit) requires about 80 k Logic elements (LUTs) = 18 k in the present Stratix 1 FPGA * 2 (to include missing functionalities) * 2 to have only 50 % loading.
This is a rough and pessimistic estimation as it is likely to be less then 80 k due to the increase of the logic element’s size within the new circuits (4 bits in Stratix 1; up to 8 bit now) and as the routing within a packed chip consumes resources.
The embedded memory is mainly used as a sine wave LUT (phase to amplitude conversion) for the 4 channels
The total memory required for this function is 352 k bits.
This memory should be available in 8 blocks of 31 kb + 8 blocks of 13 kb
Embedded memory within the MB FPGA = 352 kb per mezzanine divided in independent blocks compatible with the use described in the next slide.
A. Blas
PSB Beam Control /05/2010

6. New PSB beam control Processing power for the daughter cards
PS TFB
New PSB beam control Processing power for the daughter cards
Memory employed for each of the 4 channels
A. Blas
PSB Beam Control /05/2010