1. Apparao Kodavanti Srinivasa Guntupalli
IXP1200 Microengines
Apparao Kodavanti
Srinivasa Guntupalli

2. Network Processor
IXP 1200 is a network processor that is optimized for networking and communication applications
Has one StrongARM Core micro processor and six independent microengines.
All the processors are RISC based
C compiler and Tornado IDE for programming the StrongARM processor
Intel SDK which has a developers’ workbench for programming the microengines

4. Microengines - Architecture
The six microengines each provide the following features
Hardware multithreaded support for four contexts – context switching is non preemptive
Can hold 1024 instructions in the instruction control store
Five stage pipeline enables 1 clock cycle per instruction when fully loaded

5. Microengine - architecture
bit GPRs general purpose registers
bit transfer registers – used to transfer data from and to memory
Separate registers allow multithreading

6. Memory Hierarchy 3 different memory interfaces
Scratchpad 4k bytes cycles latency
SRAM 8MB cycles
SDRAM 256 MB cycles
Min addressable unit – 4 bytes for scratchpad and SRAM , 8 bytes for SDRAM

7. Microengine - Software
Programming Language- Microcode assembler
IXP1200 SDK has Developer’s workbench – consists of simulator, assembler , linker and debugger
Software libraries called IXP Blocks – ex- the checksum for an IP header can be calculated by using a IXP block

8. Assembler instructions
ALU , rotate and shift instructions
Branch and Jump instructions
Immediate and Load
Reference instructions – memory and hardware interfaces
Miscellaneous – hash, context switch and NOP

9. A Microcode example
Perform an endian swap on a longword, reverse the order of bytes. Used to convert big endian network bytes to little endian bytes used by IXP

10. Example code alu_shf[rswap,0,B,rbuf, <<rot8]
Byte1 byte2 byte3 byte0
ld_field[rswap,100,rbuf,<<rot24]
Byte3 byte2 byte1 byte0