1. Sequential CPU Implementation

2. Outline
SEQ timing
Organizing Processing into Stages
Suggested Reading ~ 4.3.3

3. SEQ: Sequential Processor
What is SEQ ?
SEQ: Sequential Processor
Y86 processor
Process a complete instruction in each cycle
What we have and we need?
Combinational logic and storage
ALU, Register File, Memory, PC, and CC

4. SEQ Components
Combinational Logic

5. SEQ Components
Combinational Logic
Combinational Logic
ALU

6. SEQ Components
Combinational Logic
Combinational Logic
ALU
Memory

7. SEQ Components Combinational Logic Combinational Logic Memory Memory
ALU
Memory
Memory
Register File

8. SEQ Components Combinational Logic Combinational Logic
ALU
Clocked Register
Memory
Memory
Register File

9. SEQ Components Combinational Logic Combinational Logic
ALU
Clocked Register
Memory CC
Memory
Register File PC

10. SEQ Components Combinational Logic Combinational Logic
ALU
read
write
Clocked Register
Memory CC
read
write
Memory
Register File PC

11. SEQ Components Combinational Logic ALU Control logic Memory reads
Inst. memory
Data memory
Register file
Combinational Logic
ALU
read
write
Memory CC
read
write
Register File PC

12. SEQ Components Sequential Logic (All updated as clock rises)
Program counter (PC)
Condition code (CC)
Register File
Memories
a single clock signal
(All updated as clock rises)
Combinational Logic
ALU
read
write
Memory CC
read
write
Register File PC

13. Process Instruction on SEQ
Process a complete instruction in each cycle
A single clock controls all states
Load CC and new PC
Write register file and memory
Principle只是对ISA设计的指导，不是严格的rule
因为即使是updated state总是存在于某电路上，仍然可以通过合适的设计获得的
（但是有额外的硬件开销且造成设计复杂度的提高）
The processor never needs to read back the state updated by an instruction in order to complete the processing of this instruction.

14. Beginning of Cycle 3 Clock 0x000: irmovl $0x100,%ebx # %ebx0x100
irmovl $0x200,%edx # %edx0x200
Cycle 3:
0x00c:
addl %edx,%ebx # %ebx0x300 CC000
Cycle 4:
0x00e:
je dest # Not taken

15. Beginning of Cycle 3 state set according to 2nd instruction
0x006:
irmovl $0x200,%edx # %edx0x200
Combinational Logic
ALU
state set according to 2nd instruction
PC: 0x00C
CC: 100 (assume)
%edx: 0x200
%ebx: 0x100
combinational logic starting to react to state changes
read
write
Memory
100
read
write
Register File
%ebx=0x100
%edx=0x200
0x00C

16. End of Cycle 3 Clock 0x000: irmovl $0x100,%ebx # %ebx0x100 0x006:
irmovl $0x200,%edx # %edx0x200
Cycle 3:
0x00c:
addl %edx,%ebx # %ebx0x300 CC000
Cycle 4:
0x00e:
je dest # Not taken

17. End of Cycle 3 state set according to 2nd instruction
0x00c:
addl %edx,%ebx # %ebx0x300 CC000
Combinational Logic
ALU
state set according to 2nd instruction
combinational logic generates results for 3rd instruction
read
write
Memory
100
read
write
000
Register File
%ebx=0x100
%edx=0x200
%ebx0x300
0x00C
0x00E
0x00C

18. Beginning of Cycle 4 Clock 0x000: irmovl $0x100,%ebx # %ebx0x100
irmovl $0x200,%edx # %edx0x200
Cycle 3:
0x00c:
addl %edx,%ebx # %ebx0x300 CC000
Cycle 4:
0x00e:
je dest # Not taken

19. Beginning of Cycle 4 state set according to 3rd instruction
0x00e:
je dest # Not taken
Combinational Logic
ALU
state set according to 3rd instruction
PC: 0x00E
CC: 000
%edx: 0x200
%ebx: 0x300
combinational logic starting to react to state changes
read
write
Memory
000
read
write
Register File
%ebx=0x300
%edx=0x200
0x00E

20. End of Cycle 4 Clock 0x000: irmovl $0x100,%ebx # %ebx0x100 0x006:
irmovl $0x200,%edx # %edx0x200
Cycle 3:
0x00c:
addl %edx,%ebx # %ebx0x300 CC000
Cycle 4:
0x00e:
je dest # Not taken

21. End of Cycle 4 state set according to 3rd instruction
0x00e:
je dest # Not taken
Combinational Logic
ALU
state set according to 3rd instruction
combinational logic generates results for 4th instruction
read
write
Memory
000
read
write
Register File
%ebx=0x300
0x00E
0x013
0x00E

22. Naïve Design: One-by-one
How to design SEQ ?
Naïve Design: One-by-one
Straightforward, but waste
Advanced Design: Multi-stages
Formulate instruction execution as sequence of simple steps (stages)
Like: function for programming
Best use of hardware
Challenge: use same general form for all instructions

23. Y86 Instruction Decoding5 rA rB D
icode
ifun
valC
Optional
Instruction Format
Instruction byte icode:ifun
Optional register byte rA:rB
Optional constant word valC

24. Y86 Instruction Set Byte 1 2 3 4 5 cmovle 2 1 nop cmovl 2 halt 1 cmove1 2 3 4 5
cmovle 2 1
nop
cmovl 2
halt 1
cmove 2 3
rrmovl rA,rB 2 rA rB
cmovne 2 4
cmovl rA,rB 2 fn rA rB
cmovge 2 5
irmovl V,rB 3 F rB V
cmovg 2 6
复习第一节课的内容。
rmmovl rA,D(rB) 4 rA rB D
addl 6
mrmovl D(rB),rA 5 rA rB D
subl 6 1
OPl rA, rB 6 fn rA rB
andl 6 2
xorl 6 3

25. Y86 Instruction Set Byte 1 2 3 4 5 jmp 7 jle 1 jl 2 je 3 jne 4 jge 51 2 3 4 5
jmp 7
jle 1 jl 2 je 3
jne 4
jge 5 jg 6
jXX Dest 7 fn
Dest
call Dest 8
Dest
ret 9
pushl rA A rA F
popl rA B rA F
复习第一节课的内容。

26. Instruction Execution Stages
Fetch
Read instruction from instruction memory
Decode
Read program registers
Execute
Compute value or address
Memory
Read or write data
Write Back
Write program registers PC
Update program counter
可能不是每条指令都需要执行每个阶段，而且让指令做一些它不需要的工作会降低速度。
但一个统一的框架可以将实现的复杂度降到最小。因为它们可以尽可能的共用一些部件。
比方说，ALU，如果我们允许不同的指令有不同的执行路径，那么可能就需要几个ALU来实现不同的目的。重复一些硬件电路的开销要比软件大的多。
另外，一个统一的框架也会使得处理各种特殊情况和硬件的各种古怪行为变得比较容易。

27. PC Write back Data memory Memory CC ALU CC Execute Decode Register M
A B
Register File
Register M E M
Instruction memory
Instruction
PC increment
Fetch PC

28. Fetch PC Write back Data memory Memory CC ALU CC Execute Decode
A B
Register File
Register M E M
Instruction memory
Instruction
PC increment
Fetch PC

29. Decode PC Write back Data memory Memory CC ALU CC Execute Register M
A B
Register File
Register M E M
Instruction memory
Instruction
PC increment
Fetch PC

30. Execute PC Write back Data memory Memory CC ALU CC Decode Register M
A B
Register File
Register M E M
Instruction memory
Instruction
PC increment
Fetch PC

31. Memory PC Write back Data memory CC ALU CC Execute Decode Register M
A B
Register File
Register M E M
Instruction memory
Instruction
PC increment
Fetch PC

32. Write back PC Data memory Memory CC ALU CC Execute Decode Register M
A B
Register File
Register M E M
Instruction memory
Instruction
PC increment
Fetch PC

33. PC Write back Data memory Memory CC ALU CC Execute Decode Register M
A B
Register File
Register M E M
Instruction memory
Instruction
PC increment
Fetch PC

34. SEQ Hardware Structure
Instruction Flow
Read instruction at address specified by PC: 1
Process through stages: 25
Update program counter: 6
之所以Write back阶段和PC Update阶段要回下来，是因为他们要访问Register file和PC这两个前面阶段用过的部件。
要注意的是虽然在语义动作中说各个可能写状态的阶段写状态的动作是顺序发生的。但实际上对于硬件来说，它们是同时在clock rising的时候发生的。

35. Executing arith./log. operation
opl rA, rB 6 fn rA rB
OPl rA, rB 6 fn rA rB
Fetch
Read 2 bytes
Decode
Read operand registers
Execute
Perform operation
Set Condition Ccodes
Memory
Do nothing
Write back
Update register rB
PC Update
Increment PC by 2

36. Stage Computation: arith./log. ops
OPl rA, rB
icode:ifun  M1[PC]
rA:rB  M1[PC+1]
valP  PC+2
Fetch
Read instruction byte
Read register byte
Compute next PC
valA  R[rA]
valB  R[rB]
Decode
Read operand A
Read operand B
Execute
valE  valB ifun valA
Perform ALU operation
注意：execute中的运算是valB OP valA，而不是valA OP valB
M1[PC] 表示从PC开始的内存中读取一个字节的数据。
Set CC
Set condition code register
Memory
R[rB]  valE
Write
back
Write back result
PC  valP
PC update
Update PC

37. Stage Computation: arith./log. ops
OPl rA, rB
subl %edx, %ebx 0x00c: 6123
Fetch
icode:ifun  M1[PC]
icode:ifun  M1[0x00C] = 6:1
rA:rB  M1[PC+1]
rA:rB  M1[0x00C+1] = 2:3
valP  PC+2
valP  0x00C+2 = 0x00E
Decode
valA  R[rA]
valA  R[%edx] = 9
valB  R[rB]
valB  R[%ebx] = 21
Execute
valE  valB ifun valA
valE  = 12
注意：execute中的运算是valB OP valA，而不是valA OP valB
M1[PC] 表示从PC开始的内存中读取一个字节的数据。
Set CC
ZF  0, SF  0, OF  0
Memory
Write
back
R[rB]  valE
R[%ebx]  valE = 12
PC update
PC  valP
PC  valP = 0x00E

38. PC Write back valM Data memory Memory addrs,data valE CC Cnd CC ALU CC
Execute
valA,valB
valA, valB
rA, rB
Decode
A B
Register File
Register M E M
rB,dstM
icode:ifun, rA:rB
valC
valE
valM
valP
Instruction memory
Instruction
PC increment
Fetch PC PC PC
valP