Presentation is loading. Please wait.

Presentation is loading. Please wait.

Day 25: November 7, 2011 Registers

Published byErnest Desroches Modified over 6 years ago

Similar presentations

Presentation on theme: "Day 25: November 7, 2011 Registers"— Presentation transcript:

1 Day 25: November 7, 2011 Registers
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 25: November 7, 2011 Registers Penn ESE370 Fall Mehta & DeHon

2 Previously… Clocking Discipline Follow discipline of combinational logic broken by registers Compute From state elements Through combinational logic To new values for state elements As long as clock cycle long enough, Will get correct behavior Penn ESE370 Fall Mehta & DeHon

3 Today Clocking: Register Designs Dynamic Static
Penn ESE370 Fall Mehta & DeHon

4 Gate-Latch-Register Transistor Count? Total Transistor Width?
Capacitive load on data input? Capacitive load on clock? Penn ESE370 Fall Mehta & DeHon

5 Alternate Registers Penn ESE370 Fall Mehta & DeHon

6 How does this work as a register?
Penn ESE370 Fall Mehta & DeHon

7 Compare Gate-Latch-Register
Transistor Count? Total Transistor Width? Load on input? Load on Clock(s)? Penn ESE370 Fall Mehta & DeHon

8 Weaknesses? Penn ESE370 Fall Mehta & DeHon

9 Weaknesses Hold value on capacitance (“Dynamic”) Not drive to rail
Not actively driven Easily upset by noise Will leak away eventually Sets lower bound on clock frequency Cannot “gate off” clock when not in use Not drive to rail Less noise margin More static leakage – PMOS not completely off In 2010: Had good discussion on how long before leak away. Talked about quantifying magnitude… Penn ESE370 Fall Mehta & DeHon

10 How Improve? Remember weaknesses: Holds value dynamically
Not driven to rail Penn ESE370 Fall Mehta & DeHon

11 What is the difference? Penn ESE370 Fall Mehta & DeHon

12 Transmission Gates Idea: use both NMOS/PMOS in parallel
NMOS passes the strong 0 PMOS passes the strong 1 Pass gates that swing full rail Often used in mux Penn ESE370 Fall Mehta & DeHon

13 Transmission Gate Mux How is this different from a static mux? S S 1
In1 In2 /S 2 /S S How is this different from a static mux? Penn ESE370 Fall Mehta & DeHon

14 How Improve? Remember weaknesses: Holds value dynamically
Not driven to rail Penn ESE370 Fall Mehta & DeHon

15 Level Restorer (“Staticizer”)
Penn ESE370 Fall DeHon

16 Without level restorer
This is just here to show contrast. Penn ESE370 Fall DeHon

17 With level restorer Penn ESE370 Fall DeHon

18 Level Restore What issue arises here? Penn ESE370 Fall DeHon

19 Level Restore What issue arises here? Penn ESE370 Fall2010 -- DeHon
2010: it was tricky to get them to see the ratioed logic here. Penn ESE370 Fall DeHon

20 Register with Level Restore
Penn ESE370 Fall Mehta & DeHon

21 Static Register Penn ESE370 Fall Mehta & DeHon

22 Static Register Transistors? Total width? Clock load? Input load?
Penn ESE370 Fall Mehta & DeHon

23 Comparison Gate Latch Dynamic Latch Static Latch Area Large Small
Moderate Input Cap Delay Slow Fast Dynamic No Yes Full Rail Penn ESE370 Fall Mehta & DeHon

24 Typical Static Register
Advantages: Static Full Rail Fast Phi0 Isolation inverters: Input Cap Input/Output Noise State Node Noise /Phi0 Penn ESE370 Fall Mehta & DeHon

25 Admin Midterm Review tonight at 8pm (Moore 204)
Tuesday: Andre away (no office hour) Wednesday: Midterm No lecture Midterm 7-9pm in Towne 303 New Project out Thursday: <nothing> (read project) Friday: Class (Andre) Penn ESE370 Fall Mehta & DeHon

26 Ideas Registers can be implemented more compactly with pass transistor-based designs Penn ESE370 Fall Mehta & DeHon

Download ppt "Day 25: November 7, 2011 Registers"

Similar presentations

Pass Transistor Logic. Agenda  Introduction  VLSI Design methodologies  Review of MOS Transistor Theory  Inverter – Nucleus of Digital Integrated.

Pass Transistor Logic. Agenda  Introduction  VLSI Design methodologies  Review of MOS Transistor Theory  Inverter – Nucleus of Digital Integrated.
Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Memory elements. n Basics of sequential machines.

Modern VLSI Design 4e: Chapter 5 Copyright  2008 Wayne Wolf Topics n Memory elements. n Basics of sequential machines.
Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 4, 2011 Synchronous Circuits.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 4, 2011 Synchronous Circuits.
S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN1600) Lecture 21: Dynamic Combinational Circuit Design Prof. Sherief Reda Division of.
Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Memory elements. n Basics of sequential machines.

Modern VLSI Design 2e: Chapter 5 Copyright  1998 Prentice Hall PTR Topics n Memory elements. n Basics of sequential machines.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 5, 2014 Dynamic Logic Midterm.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 12, 2014 Memory Core: Part.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 30: November 12, 2014 Memory Core: Part.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors.
Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 14, 2011 Memory Core.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 14, 2011 Memory Core.
Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 5, 2010 Memory Overview.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 5, 2010 Memory Overview.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 26: October 31, 2014 Synchronous Circuits.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 26: October 31, 2014 Synchronous Circuits.
Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: November 1, 2010 Dynamic Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: November 1, 2010 Dynamic Logic.
Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 33: November 20, 2013 Crosstalk.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 33: November 20, 2013 Crosstalk.
Penn ESE370 Fall2011 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 31, 2011 Pass Transistor Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 31, 2011 Pass Transistor Logic.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 22, 2014 Pass Transistor Logic.
Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 7, 2014 Memory Overview.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 7, 2014 Memory Overview.
Penn ESE370 Fall2013 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 8, 2013 Memory Overview.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 28: November 8, 2013 Memory Overview.
Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 19, 2012 Ratioed Logic.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 19, 2012 Ratioed Logic.
Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 5, 2012 Synchronous Circuits.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 24: November 5, 2012 Synchronous Circuits.
Penn ESE370 Fall2010 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 20: October 25, 2010 Pass Transistors.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 20: October 25, 2010 Pass Transistors.

Similar presentations

Ads by Google