1. BIC 10503: COMPUTER ARCHITECTURE
Chapter 2 Bus System

2. Overview
2.1 Components of a computer 2.2 Functions of a computer 2.3 Interrupts

3. 2.1 Components of a Computer

4. Program Concept Hardwired program are inflexible
Hardwired program is a configuration of logic components which is constructed to perform a particular computation.
General purpose hardware can do different tasks, given correct control signals
Instead of rewiring, supply a new set of control signals
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5. Hardware and Software Approaches
How to implement this arithmetic operation using hardwire and software
X=pow(2,3); //

6. For each step, an arithmetic or logical operation is done
What is a program?
A sequence of steps
For each step, an arithmetic or logical operation is done
For each operation, a different set of control signals is needed
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7. 2.2 Functions of a Computer

8. Function of Control Unit
For each operation a unique code is provided
e.g. ADD, MOVE
A hardware segment accepts the code and issues the control signals
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9. Data and instructions need to get into the system and results out
Components
The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit
Data and instructions need to get into the system and results out
Input/output
Temporary storage of code and results is needed
Main memory
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10. Computer Components: Top Level View
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11. How Instruction is Executed?
What is instruction?
Instruction specify the action that the processor is suppose to take.
The processing required for a single instruction is called an instruction cycle.
Instruction cycle are made of these two steps:
Fetch (processor reads from memory and also referred to as fetch cycle)
Execute (Also referred to as execute cycle)
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12. Program Counter (PC) holds address of next instruction to fetch
Fetch Cycle
Program Counter (PC) holds address of next instruction to fetch
Processor fetches instruction from memory location pointed to by PC
Increment PC
Unless told otherwise
Instruction loaded into Instruction Register (IR)
Processor interprets instruction and performs required actions
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13. Execute Cycle
An instruction’s execution (execute cycle) may involve one or a combination of these actions
Processor-memory
data transfer between CPU and main memory
Processor I/O
Data transfer between CPU and I/O module
Data processing
Some arithmetic or logical operation on data
Control
Alteration of sequence of operations
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14. Instruction Format Assume both instructions and data are 16 bits long.
The instruction format provides
4 bits for the opcode, so that there can be as many as 24 = 16 different opcodes and
12 bits for the address , so that up to 212 words of memory can be directly addressed.
Instruction format
Integer format
Figure 3.4 Characteristics of a Hypothetical Machine

15. Example of Program Execution
Internal CPU Registers
PC (Program Counter)
AC (Accumulator)
– a data register
IR (Instruction Register)
Program to be executed:
Adds the content of the
memory word at address
940 to the content of the
memory word address
941 and stores the result
in latter location.
Figure 3.5 Example of Program Execution
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16. (cont.) Example of Program Execution
Requires 3 fetch and 3 execute
cycles.
{1st Fetch cycle} The PC contains 300, the address of the first instruction. This instruction (the value 1940 in hexadecimal) is loaded into the instruction register IR and the PC is incremented. Note that this process involves the use of a memory address register (MAR) and a memory buffer register (MBR). For simplicity these intermediate registers are ignored.
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17. (cont.) Example of Program Execution
{1st Execute cycle} The first
4 bits (first hexadecimal digit) in the IR indicate that the AC is to be loaded. The remaining 12 bits (3 hexadecimal digits) specify the address (940) from which data are to be loaded.
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18. (cont.) Example of Program Execution
{2nd Fetch cycle} The next instruction (5941) is fetched from location 301 and the PC is incremented.
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19. (cont.) Example of Program Execution
{2nd Execute cycle} The old content of the AC and the content of location 941 are added and the result is stored in the AC.
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20. (cont.) Example of Program Execution
{3rd Fetch cycle} The next instruction (2941) is fetched from location 302 and the PC is incremented.
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21. (cont.) Example of Program Execution
{3rd Execute cycle} The content of AC is stored in location 941.
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22. Instruction Cycle State Diagram
The upper part involve an exchange between the processor and memory or between processor and I/O module.
States in the lower part of the diagram only internal processor operations.
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23. 2.3 Interrupts

24. Why Use Interrupts?
Other modules (e.g. I/O, memory) may interrupt the processor’s normal sequence of processing.
Interrupts are provided primarily as way to improve processing efficiency.
The processor can be used for processing something else (e.g. open and edit a Word document) while I/O operation (e.g. printing) is in progress.
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25. Classes of Interrupts Program Timer I/O Hardware failure
e.g. due to overflow, division by zero
Timer
Generated by internal processor timer
Used in pre-emptive multi-tasking (do certain function in regular basis e.g. data backup)
I/O
from I/O controller to signal normal completion or error conditions.
Hardware failure
e.g. power failure, memory parity error

26. Program Flow Control
X – interrupt occurs during course of execution of user program
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27. (cont.) Program Flow Control
The user program perform a series of WRITE calls interleaved (berselang-seli) with processing.
Code segment 1, 2 and 3 refer to sequences of instructions that do not involve I/O.
The WRITE calls are to an I/O program that is a system utility and that will perform the actual I/O operation.
The I/O program consists of 3 sections:
Label 4: sequence of instructions to prepare for actual I/O.
The actual I/O (Processor WAIT for this to finish).
Label 5: sequence of instructions to complete the I/O operation. May include setting flag indicating success or fail.

28. Interrupt Cycle Added to instruction cycle
(NOW Instruction Cycle = Fetch Cycle + Execute Cycle +
Interrupt Cycle)
Processor checks for interrupt
Indicated by an interrupt signal
User program does not have to contain special code for handling interrupt
The processor and operating system are responsible for suspending user program
If no interrupt, fetch next instruction
If interrupt pending:
Suspend execution of current program
Save context (save next instruction address and other data relevant to processor’s current activity)
Set program counter (PC) to start address of interrupt handler routine
Process interrupt
Restore context and continue interrupted program
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29. Transfer of Control via Interrupts
When the interrupt handler routine is completed, the processor can resume execution of the user program at the point of interruption.

30. Instruction Cycle with Interrupts
If no interrupts are pending, processor proceeds with the fetch cycle and fetches the next instruction of the current program.
If interrupt is pending, the processor will do the followings:
It suspends execution of the current program and saves its context (save next instruction address and other data relevant to processor’s current activity).
Sets the program counter to the starting address of an interrupt handler routine. Interrupt handler program is generally part of operating system.

31. Program Timing: Short I/O Wait
Program Timing with Short I/O Wait
For the system using interrupts, the time required for the I/O operation is relatively short: less than the time to complete the execution of instructions between 2 WRITE operations in the user program.
Thus, with interrupt (Figure b) no waiting time by the processor.

32. Program Timing: Long I/O Wait
Program Timing with Long I/O Wait
For WRITE I/O operation taking longer wait time, longer than the time to complete the execution of instructions between 2 WRITE operations in the user program.
The first WRITE I/O need to be completed first before the second WRITE can be processed.

33. Instruction Cycle (with Interrupts) - State Diagram
(Compare with “Instruction Cycle State Diagram” in slide 26)
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34. Multiple Interrupts Approaches to Deal with Multiple Interrupts
Disable interrupts
Processor will ignore further interrupts whilst processing one interrupt
Interrupts remain pending and are checked after first interrupt has been processed
Interrupts handled in sequence as they occur
Used in Multiple Interrupt - Sequential
Define priorities
Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns to previous interrupt
Used in Multiple Interrupt - Nested
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35. Multiple Interrupts - Sequential
Disable Interrupt Approach
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36. Disable Interrupt Approach
Advantage
Nice and simple
Disadvantage
Does not take into account relative priority and time-critical needs.

37. Multiple Interrupts – Nested
Define Priorities Approach
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38. Time Sequence of Multiple Interrupts

39. (cont.) Time Sequence of Multiple Interrupts

40. Interrupt - Exception
No interrupt is required for operation not involving processor e.g. DMA (Direct Memory Access).
In some cases, I/O devices can operate directly with memory without depending on processor.
When processor is bypassed (not using processor), then interrupt is not needed.
Direct memory access (DMA) can be used for data exchanges between I/O device and memory (not controlled by processor).

41. Exercise 1
Due date: Next week

42. THANK YOU