Sungho Kang Yonsei University

Sungho Kang Yonsei University
Built In Self Test Sungho Kang Yonsei University

Outline Introduction Pattern Generation Response Analysis
BIST Architectures Conclusion

Built In Self Test Introduction Capability of a product to carry out an explicit test of itself Test patterns are generated on-chip Responses to the test patterns are also evaluated on chip External operations are required only to initialized the built-in tests and to check the test results (go/no-go)

Built In Self Test Advantage Disadvantages
Introduction Advantage No need for expensive tester At-speed testing Thorough test Disadvantages Initial Design Investment Area overhead Pin overhead Not effective for random testing resistive circuits Aliasing problem

Test Pattern Generation
Stored Pattern Exhaustive Pattern Pseudo Exhaustive Pattern Pseudo Random Pattern Weighted Random Pattern

Stored Pattern Store deterministic test patterns in a ROM
Pattern Generation Store deterministic test patterns in a ROM Can achieve high fault coverage Requires large memory space Requires external ATPG and fault simulation Not practical or cost effective for large circuits

Exhaustive Pattern Pattern Generation For n input combinational circuit, 2n exhaustive patterns are required For large n, it is not practical Detects all irredundant, combinational faults Uses binary counters or LFSRs

Exhaustive and Pseudo Exhaustive
Pattern Generation Possible required Fault free simulation Way to make segmentation Not required Fault simulation Circuit modification Very high fault coverage Pattern generation Use counters or LFSRs

Pseudo Exhaustive Pattern
Pattern Generation Used when exhaustive test is too long Divide circuits into subcircuits Individual output verification (Cone verification) Exhaustive test of each output No output depends on all inputs Segment verification Network partitioned Exhaustive test of each segment

Combinational Circuit Classification
Pattern Generation Partial Dependence Circuit (PDC) No output depends on all inputs Exhaustive test if possible Else output verification test Else segment verification Full Dependence Circuit (FDC) Some output depends on all inputs

Cone Verification Pattern Generation The p output circuit is logically divided into p cones Each cone is tested exhaustively All cones are tested concurrently (n,w) CUT n inputs and output Yi = fi(Xi), w = maxi { |Xi| } Example : (4,2) CUT If w=n, pseudo exhaustive testing is exhaustive testing

Cone Verification LS630 (16bit error detection and correction)
Pattern Generation LS630 (16bit error detection and correction) 24 inputs, 6 outputs Each output depends on 10 inputs 210 patterns for each output 6 X 210 patterns for all

PDC Classification MTC Maximal Test Concurrency Circuit
Pattern Generation MTC Maximal Test Concurrency Circuit The number of test signals required The maximum number of inputs connected to any output MTC Example 4 test vectors required A = C Minimal number of required test signals is equal to the maximum number of inputs upon which any output depends

PDC Classification NMTC Non-Maximal Test Concurrency Circuit
Pattern Generation NMTC Non-Maximal Test Concurrency Circuit The number of test signals required More than the maximum number of inputs connected to any output NMTC Example Every output is a function of only 2 inputs Each output can still be tested exhaustively by patterns

PDC Classification NMTC Example
Pattern Generation NMTC Example Every output is a function of only 2 inputs Each output can be tested exhaustively by 5 patterns

NMTC Identification of minimal set of test signals
Pattern Generation Identification of minimal set of test signals Partition the circuit into disjoint subcircuits For each disjoint subcircuit Generate a dependency matrix Partition the matrix into groups of inputs so that 2 or more inputs in a group do not affect the same output Collapse each group to form an equivalent input, called a test signal input Characterize the collapsed matrix in terms of p and w where p is the number of partitions (width) and w is the maximum number of 1s in any row (weight) Construct the test pattern for the circuit p=w : MTC and test set consists of all 2p patterns p=w+1 : test set consists of all possible patterns of p with either odd or even parity p>w+1 : test set consists of 2 or more pattern subsets, each of which contains all possible patterns of p bits having a specific constant weight

NMTC Example Example circuit Dependency matrix
Dij = 1 if output I depends on input j ; otherwise Dij=0

NMTC Example Reordering and grouping the inputs produce the following modified matrix

NMTC Example In each group there must be less than two 1s in each row and the number of groups should be minimal This insures that no output is driven by more than one input from each group Finding such a partition is NP-complete ORing each row within a group to form a single column

NMTC Example p=4 and w=3 odd parity A B C D 0 0 0 1 0 0 1 0 0 1 0 0
Pseudo exhaustive test set consists of 8 patterns instead of 128 Among 4 groups, 8 patterns using any 3 inputs are necessary

NMTC Total number of test patterns is a function of p and w
Constant weights do not exist for all pairs of p and w For such cases, w can be increased so as to achieve a constant-weight pseudo exhaustive test, but it may not be minimal in length It is always easy to construct a circuit to generate a pseudo exhaustive test set for p>w+1 and hardware overhead of some of these circuits is quite high

Segment Verification Segmentation testing via path sensitization
Pattern Generation Segmentation testing via path sensitization Sensitized path is established from C to F Use 2n1+2n2 patterns instead of 2n1+n2 patterns

FDC LS181 (ALU) Use segmentation 14 inputs, 8 outputs
Pattern Generation LS181 (ALU) 14 inputs, 8 outputs Some outputs depends on all inputs 214 patterns Use segmentation Only 356 patterns are required

Segment Example Exhaustive test vectors : 64
Pattern Generation Example Exhaustive test vectors : 64 Output cone test vectors : 32

Segment Example Pattern Generation Example

Segment Example Exhaustive test of G sensitized to F2 by Z = 1
Pattern Generation Exhaustive test of G sensitized to F2 by Z = 1 U V W X Y Z G H F1 F2

Segment Example Added to exhaustive test of G U V W X Y Z G H F1 F2
Pattern Generation Added to exhaustive test of G U V W X Y Z G H F1 F2

Segment Example Added to exhaustive test of H U V W X Y Z G H F1 F2
Pattern Generation Added to exhaustive test of H U V W X Y Z G H F1 F2

Segment Example Added to exhaustive test of F1 U V W X Y Z G H F1 F2
Pattern Generation Added to exhaustive test of F1 U V W X Y Z G H F1 F2

Segment Example Segmentation by multiplexors Path sensitization : 10
Pattern Generation Segmentation by multiplexors Path sensitization : 10 Multiplexors : 13

Segment 74181 ALU 214 exhaustive patterns
Pattern Generation 74181 ALU 214 exhaustive patterns Output cone test : 214 patterns

Segment Pattern Generation 74181 ALU Li function : 16 patterns

Segment Pattern Generation 74181 ALU Hi function : 16 patterns

Segment 74181 ALU 74181 ALU : N2 Hi = (Ai X Bi)’ Li = Ai’
Pattern Generation 74181 ALU 74181 ALU : N2 Hi = (Ai X Bi)’ Li = Ai’ Design constraints : HiLi = 01 is impossible 34 AB tests X 22 M Cn tests : 324 Segment Test : = 356

Pseudo Exhaustive Pattern
Pattern Generation 8 input parity tree Instead of 256 pattern, only 4 patterns are required Minimum pseudo exhaustive pattern a b c d e f g h i j k l m n

Constant Weight Pseudo Exhaustive
Pattern Generation Any (n, w) circuit can be tested by a constant weight counter implementing a w-out-of-k code for an appropriate value of k n : number of inputs w : weights maximum of inputs for any cone 2-out-of-4 code 1100 1010 1001 0110 0101 0011

Pseudo Random Pattern Test Pattern Source
Pattern Generation Test Pattern Source ALFSR (Autonomous Linear Feedback Shift Register) LFSR All patterns equally likely Sometimes misnamed random

Random vs Pseudorandom
Pattern Generation Random Patterns can occur more than once Non-reproducible Pseudorandom All (possibly except all-0 pattern) patterns occur before any pattern repeats Reproducible

Linear Feedback Shift Register
Pattern Generation The state of shift register depends only on the prior state

Pattern Generation Polynomial shorthand notation for a bit stream x6+x2+x+1 1X6+0X5+0X4+0X3+1X2+1X+1 Arithmetic of polynomial is modulo 2 Addition and subtraction is the same (x-1) is the same as (x+1) Degree of a polynomial is the highest power of the non-zero term

Pattern Generation Generating function G(x) G(x) = a0+a1x+a2x2+…+amxm+... = amxm where ai is 0 or 1 For type 1 LFSR

Pattern Generation Characteristic polynomial P(x) P(x) = 1+c1x+c2x2+…+cnxn If a-1=a-2=…=a1-n=0 and a-n=1 then

Pattern Generation Maximum length sequence Period of 2n-1 for n stage LFSR Disregard all 0's Primitive polynomial Characteristic polynomial with a maximum length sequence Non Primitive Polynomial Less than maximal length Irreducible polynomial Not divisible by any other polynomial other than 1 and itself Has an odd number of terms including the 1 term If its degree n is greater than 3, the P(x) must divide into 1+xk where k = 2n-1 Example x4+x3+1 divides evenly into X15+1

Pattern Generation Number of Primitive Polynomials n PPs n PPs

Pattern Generation Primitive Polynomial n Primitive Polynomial 1, 2, 3, 4, 6, 7, 15, x+xn 5, 11, 21, x2+xn 10, 17, 20, 25, 28, x3+xn x4+xn x5+xn x7+xn x2+x3+x4+xn x+x4+x6+xn x+x3+x4+xn 14, x3+ x4+x5+xn 19, x+x2+x5+xn x+x2+x7+xn x+x2+x6+xn x+x2+x23+xn x+x2+x22+xn

Pattern Generation Pseudo Random Pattern Generation Characteristic Polynomial : 1+x2+x3 Initial condition (1,0,0) : x Q1 : x / (1+x2+x3) Q2 : x2 / (1+x2+x3) Q3 : x3 / (1+x2+x3)

Pattern Generation When initial state is 100 Q1 Q2 Q3

Pattern Generation When initial state is 000 Q1 Q2 Q3

Combined LFSR and SR Less cost than constant weight counter
Pattern Generation Less cost than constant weight counter

Combined LFSR and XOR Close to LFSR/SR Q1 Q2 Q3 Q4 1 0 0 1 0 1 0 0
Pattern Generation Close to LFSR/SR Q1 Q2 Q3 Q4

Condensed LFSR Efficient when w >= n/2
Pattern Generation Efficient when w >= n/2 When w < n/2, use combined LFSR and SR

Cyclic LFSR When w < n/2 Condensed LFSR Combined LFSR and XOR
Pattern Generation When w < n/2 Condensed LFSR Produce long test length for (n,w) circuits Combined LFSR and XOR Have a high hardware overhead Use cyclic code Low hardware overhead and reduce test length

LFSR for Exhaustive Test
Pattern Generation Include NORs

Weighed Random Patterns
Pattern Generation All patterns not equally likely Pseudo random test patterns are inefficient when random-pattern-resistant faults exist. Make Prob[1]  Prob[0] at pattern sources Random resistant faults Consider a 32 input AND and output s-a-1 fault The output s-a-1 is detected when all inputs are 1 When pseudo random testing is used, the detection probability is 1/232

WRPG Let pf be the detection probability of fault f
(1- pf)N : probability that f is not detected by N independent patterns C = 1-(1- pf)N : Confidence of detecting f by a random test set of N patterns. N = ln(1-C)/ln(1- pf) : # of patterns to reach Confidence C. The test length required for detecting a set of faults F only depends on the fault f with the lowest detectability. Example> 32-input AND gate Pseudo random testing 4.48 X 1010 patterns required to reach C = 0.999 WPRG When the probability of 0 is 1/232 pf = 0.5, N=600

Multiple Weight Sets Consider a circuit with a 32 input AND and a 32 input OR where the same 32 inputs feed them Consider AND output s-a and OR output s-a-0 If the same weights are applied, one of two faults are hard to detect. It is necessary to have different weight sets (1/232, 1-1/ 232) (1-1/ 232, 1/ 232)

Multiple Weight Sets The efficiency of multiple weight set is determined by both the number of weight sets (r), and the total number of random test patterns to be applied (N). The goal of weight generation is to reduce both r and N

Multiple Weight Sets Single weight set Multiple weight sets Advantage
Small hardware overhead Disadvantages Low fault coverage Long test pattern length Multiple weight sets Advantages High fault coverage Short test pattern length Large hardware overhead

Weight Generation Methods
Structural analysis Small number of patterns and weight sets Easy implementation Poor fault coverage Deterministic test sets All non-redundant faults can be detected A high number of random patterns and weights Large hardware overhead Combined both methods

Maximizing Don’t Cares
If “Don’t Cares” occur in a test set they must not contribute to the weights by maximizing the number of “Don’t Care” bits , ATPG can remove redundancies in the test set

Maximizing Don’t Cares
Decisions are guided by a number of heuristics which particularly aim at generating test patterns with a large number of unspecified bits, and keeping the overall test set small For error propagation, a node on the D-frontier is selected which is as close as possible to the POs and is located on a path with a maximum number of undetected faults, For line justification, observability are used if there is a choice of a gate input line to be set to a controlling value if the gate output is observable a gate input line is selected such that the number of undetected faults preceding this line is maximum if not observable a gate input line is selected such that the number of primary inputs to be set becomes minimal

ATPG and Weight Generation
A) ATPG is performed for all the undetected faults. ATPG tries to maximize the number of “Don’t Cares” B) Weight generation C) WRPG and fault simulation Pattern generation is stopped if the last k successive patterns do not detect any new fault. ( k = a user-defined parameter) B’) Weight computation by using Hamming distance Resolving conflicts Only the patterns from D(t,T,m) are used for weight generation reversing weight generation

Comments Pseudo Random Test Pattern could be proved to be inefficient when Random-pattern-resistant faults exist. Weight set generation methods can be based on the structural analysis or deterministic test sets. If possible, the small number of weight sets, the small number of total test patterns, and High fault coverage should be achieved at the same time. To combine advantages of both methods, Weight generation and ATPG could be integrated. Maximize the number of “Don’t Cares” in deterministic sets. Resolving conflict information problem by partitioning deterministic test patterns in actually testing ,WRP is generated by circuits consisting of LFSR and combinational logic. Rounding of weights

Response Analysis Duplication Ones Count Transition Count Parity Check
Syndrome Signature Analysis

Duplication Comparison of outputs of 2 implementations
Response Analysis Comparison of outputs of 2 implementations Can avoid alias problem Can avoid loss of effective fault coverage of a signature analyzer Hardware overhead

Compression Signature : output of the compactor Decision factors
Response Analysis Signature : output of the compactor Decision factors Extra hardware Loss of fault coverage Calculation of good signature Aliasing A faulty circuit produces a signature that is identical to the signature of a fault free circuit

Ones Count Count the number of ones at the output
Response Analysis Count the number of ones at the output After applying n vectors, the signature is between 0 and n Masking probability Prob(masking) = ( nCp - 1 ) / (2n - 1)

Transition Count Signature
Response Analysis Signature The number of 0-to-1 and 1-to-0 transitions at the output After applying n vectors, signature is between 0 and n-1 Masking probability Prob(masking) = 2 X (n-1)Cp / (2n-1) p : the number of transitions in a fault free response

Parity Check Signature : parity
Response Analysis Signature : parity Compression circuit consists of a XOR and a D FF LFSR with G(x) = x + 1 Masking probability Prob(masking) = ( 2(n-1) - 1 ) / (2n - 1)

Syndrome All 2n patterns are applied to the input
Response Analysis All 2n patterns are applied to the input The number of 1's at an output is counted Compare the number of 1's for good machine and for faulty machine Syndrome S = k/2n k : the number of minterms n : the number of inputs Normalized number of ones at the output Not all Boolean functions are totally Syndrome testable Used for exhaustive testing

Syndrome No reconvergent fanout Reconvergent fanout C3 Syndrome of S3
Response Analysis No reconvergent fanout C Syndrome of S3 AND S1S2 NAND S1S2 OR S1 + S2 - S1S2 NOR ( S1 + S2 - S1S2) XOR S1 + S2 - 2S1S2 Reconvergent fanout C Syndrome of S3 AND S1 + S2 + S((FG)’) - 1 OR S1 + S2 - S(FG) XOR S( F’G) + S(FG’)

Signature Analysis Compaction of Test Data in a LFSR
Response Analysis Compaction of Test Data in a LFSR How to compare the results? Applying test sequence and compare signature Signature value left in LFSR To obtain signature and initialization pattern, use a golden board Aliasing Fault free signature is the same as fault signature Probability : 1/2n

Signature Analysis Response Analysis

Signature Analysis Initial Value : 000 Good Good Faulty Faulty
Response Analysis Initial Value : 000 Good Good Faulty Faulty Patterns Responses Patterns Responses Z1 Z2 Z3 Q1 Q2 Q Z1 Z2 Z3 Q1 Q2 Q3

Aliasing Initial Value : 000 Good Good Faulty Faulty
Response Analysis Initial Value : 000 Good Good Faulty Faulty Patterns Responses Patterns Responses Z1 Z2 Z3 Q1 Q2 Q Z1 Z2 Z3 Q1 Q2 Q3

Aliasing Response Analysis For the register length n and the length of test bit stream m, assume that all possible bit streams are evenly distributed over all possible signatures The number of bit stream that produce a specific signature is 2m/2n = 2m-n For a particular fault-free response, there are 2m-n -1 erroneous bit stream with same signature Since there are a total of 2m-1 possible erroneous response streams, the aliasing probability is (2m-n-1)/(2m-1) = 2-n Reduce aliasing Increase the length of register chain Access signature several times

Signature Analysis Response Analysis Parallel Faster Serial

MISR Response Analysis Normally, a single input signature analyzer is not used due to testing overhead Aliasing Probability : 1/2n All error patterns are equally likely

Using ALU Response Analysis Low Overhead

Alias Probability Response Analysis P (fault not detected) = P(no output error) + P(output error | correct signature) P (fault not detected) = P(no output error) P(output error) P(correct signature | output error) P (no output error) escape probability P (correct signature output error ) alias probability (PAL)

PAL Depends on Exact calculation of PAL is NP-complete
Response Analysis Depends on P : characteristic of fault and circuit L : test length f(x) : polynomial describing signature register Exact calculation of PAL is NP-complete Bound for Serial Signature Analysis PAL <= (1+e)/L if L < Lc PAL <= 1 if L = h X Lc PAL <= 2/(L2+1) if L>Lc and L h X Lc Lc signature register period maximum autonomous cycle length What we want Alias probability upper bound, independent of P Use signature polynomial with period test length

BIST Structures On-line BIST
Architectures On-line BIST Testing occurs during normal operating conditions Self checking Off-line BIST Embedded Use system registers to generate and compact test data Separate Use registers external to the system function to generate and compact test data Centralized Several CUTs share TPG and ORA Distributed

BIST Structures Decision factors Degree of test parallelism
Architectures Decision factors Degree of test parallelism Fault coverage Level of packaging Test time Physical constraints Complexity of replaceable units Performance degradation

Separate BIST Drawbacks Advantages Danger Long test time Poor delay
Architectures Drawbacks Long test time Poor delay Advantages Low overhead Simple control logic Danger Decimation Dependency Linear Dependency

Decimation Dependency
Architectures The number of LFSR patterns, M 2m or 2m-1 The number of possible different scan path patterns, P Minimum of the followings M N=2n ( LCM of M and n )/n = M / (GCD of M and n) Example m=4, M=15, n=5 : P=3 m=10, M=1023, n=9 : P=341

Linear Dependency If n < m If n >= m and kj < m
Architectures If n < m No linear dependency If n >= m and kj < m If n >= m and kj >= m Possible linear dependency

CSBL Centralized and separate board level BIST No boundary scan
Architectures Centralized and separate board level BIST No boundary scan Best suited for not many feedbacks Fault simulation is required to determine the number of test vectors to achieve an adequate level of fault coverage

LOCST LSSD On-Chip Self Test Centralized and separate BIST
Architectures LSSD On-Chip Self Test Centralized and separate BIST Scan path (LSSD) Boundary scan On-chip test controller

STUMPS Self Testing Using MISR and Parallel SRSG
Architectures Self Testing Using MISR and Parallel SRSG Centralized and separate BIST Multiple scan paths Reduction in test time No boundary scan Lower overhead than BILBO but takes longer to apply

CBIST Concurrent BIST Centralized and separate BIST
Architectures Concurrent BIST Centralized and separate BIST No scan or boundary scan Can be used for sequential logic On-line testing PRPG and MISR are initialized until Enable signal is enabled Off-line testing PRPG drives the circuit and responses are compressed in MISR

CEBS Centralized and Embedded BIST with Boundary Scan
Architectures Centralized and Embedded BIST with Boundary Scan The first r bits of the input boundary scan registers are used for PRPG and the last s bits are used for MISR or SISR

Random Test Data Distributed and embedded BIST Boundary scan
Architectures Distributed and embedded BIST Boundary scan Some binary patterns are repeated Others may not be generated R1 and R2 : PRPG R2 and R3 : MISR

Simultaneous Self-Test
Architectures Distributed and embedded BIST Scan path No LFSR No boundary scan Problem in testing external logic Problem in characterizing the quality of test process

Simultaneous Self-Test
Architectures Use self-test storage cell for each storage cell Normal mode : Q = D Test mode (self test) : Q = D  Si Test Mode=1 Scan mode Test Mode=0

Cyclic BIST Architectures Use sequential circuits as nonlinear binary sequence generators If there are more outputs than inputs, extra outputs can be combined using XOR Low area overhead Effectiveness is circuit dependent Asynchronous feedbacks are possible CUT should be clocked a predetermined times (determined by fault simulation)

Circular BIST General architecture Register based Partial self test
Architectures General architecture Register based Partial self test All inputs and outputs must be associated with boundary scan cell All storage cell must be initializable before testing LFSR with primitive polynomial 1+xn

Circular BIST Storage Cell [A] [B] N/T Z Mode 0 Dj System
Architectures Storage Cell [A] N/T Z Mode 0 Dj System 1 Dj  Sj-1 Test [B] B0 B1 Z Mode Reset Sj Scan Dj System Dj  Sj-1 Test

Circular BIST Test process Initialization Testing of circuit
Architectures Test process Initialization Testing of circuit Response evaluation

Circular BIST Advantages Disadvantages High fault coverage
Architectures Advantages High fault coverage Low hardware overhead One test per clock Disadvantages Pattern generation is heavily dependent of the circuit function Certain pattern may be generated May be used with partial scan path to apply deterministic patterns

Scan Dependence Possible if use output of MISR as test patterns
Architectures Possible if use output of MISR as test patterns FF (i+1) is scan dependent iff during normal operation it is functionally dependent on the previous FF(i) in the scan path

Scan Dependence Example
Architectures Example Normal mode : Zi+1 = Qi + f MISR mode : Zi+1 = Qi’f : incorrect Yi+1 is scan dependent if Yi+1 is a function of Yi Eliminate scan dependence by reordering scan path Use scan dependence to reduce BIST overhead Redesign scan cell for scan dependence bits

BILBO(Built-In Logic Block Observer)
Architectures Take advantage of the register aspects of many design Program counter, instruction register, accumulator Normal registers are replaced by BILBO register Inputs to a logic C are driven by a BILBO register Output of C drives another BILBO register

BILBO(Built-In Logic Block Observer)
Architectures B1 B2 Mode Normal Mode Reset Shift Register Signature Analyzer

BILBO Operations Architectures Shift Register Mode : B1=B2=0

BILBO Operations Architectures Normal Mode : B1=B2=1

BILBO Operations Signature Analysis Mode : B1=1 B2=0
Architectures Signature Analysis Mode : B1=1 B2=0 If Z1=Z2= … =Zn=0, PRPG

BILBO To test A To test B R1 : RPG R2 : Signature Analyzer R2 : RPG
Architectures To test A R1 : RPG R2 : Signature Analyzer To test B R2 : RPG R1 : Signature Analyzer

Bus Oriented BILBO Architectures In PRPG mode, BILBO register need to be held at constant value by disabling all bus drivers and using pull-up or pull-down circuitry

BILBO Pipeline Architectures Need to deactivate inputs to BILBO registers during PRPG mode

BILBO Advantages Drawbacks Danger At-speed test Reuse system bistables
Architectures Advantages At-speed test Reuse system bistables Drawbacks Multiple Test sessions Complex control Danger Register self-adjacency

Register Self-Adjacency
Architectures A register Ri is said to be a driver of a logic C if some outputs of Ri are inputs to C A register Rj is said to be a receiver of C if some outputs if C are inputs to Rj Ri is said to be adjacent to Rj if there exists a block of logic C such that Ri is a driver of C and Rj is a receiver of C If Ri is both a receiver and a driver of C, it is self-adjacent Avoid by design or synthesis Use Concurrent BILBO

Concurrent BILBO Architectures Register can be operated as PRPG and MISR simultaneously B1 B2 Mode Normal Scan PRPG/MISR

Test Schedule Test session Test scheduling problem
Architectures Test session An assignment of test modes to BILBO registers to test one or more blocks Test scheduling problem Determine the minimal number of test sessions required to test all blocks of combinational logic Determine the minimal colors that can be assigned to the nodes of a graph such that no edge connects two nodes of the same color More complex when the test time for each block is considered

Partial BILBO Pipeline
Architectures Only a subset of registers are made for BILBO Reduction on hardware complexity

Control of BILBO Architectures When multiple test sessions exist, the efficient control becomes important The first cell of BILBO register and the control lines to all the cells are driven by the above logic S* drives the S0 to the first cell in BILBO register T0 T1 T2 Mode B0 B1 S* PRPG FB MISR FB Q SHIFT Q X LATCH X RESET X

Control of BILBO Control Sequence
Architectures Control Sequence Inhibit system clocks and enter the test mode Initialize control registers with data specific to a test session Send the LFSRs and scan paths Initiate the test process Process the final signature to determine if an error has been detected

STARBIST Each cluster contains one parent test vector in the center
Architectures Each cluster contains one parent test vector in the center A number of children patterns is derived from parent test vector by complementing certain number of coordinates in pseudo-random pattern This method doesn’t use the conventional LFSR directly to generate pseudo-random patterns The implementation makes use of scan order and polarity between the neighboring scan cells

Phase Shift BIST Partition circuit into NAC and scan chain
Architectures Partition circuit into NAC and scan chain NAC(Nearly Acyclic Circuit) sequential synchronous circuit the period of which is not larger than 1 Pseudo random patterns by LFSR and PS are applied through primary inputs and scan chain PS(Phase Shifter) required to avoid the structural dependency between outputs of pattern generator Compress output values using MISR and SC(Space Compressor)

Phase Shift BIST Architectures

Multiple Fixed Biased PR BIST
Architectures Pattern is applied to CUT (Circuit Under Test) through n idler register segment Idler register segment is operated by BIST pattern generation and control logic Each idler register segment has a different biasing value and some bits are fixed to a specified value The output of CUT is passed to MISR and fault identification is performed using signature that remains in MISR

Multiple Frequency Scan BIST
Architectures Several scan chains is synchronized in different frequencies Each frequency is generated by system clock and primary inputs To synchronize different scan chains, clock number required to load scan chain and perform sampling must be divided by the ratio of any frequency pair BIST core is composed of random pattern generator, signature analyzer, pattern counter, scan mode signal generator, and clock generator Better performance than STUMPS

Multiple Frequency Scan BIST
Architectures

Conclusion Conclusion In BIST, the test pattern generation and the output response evaluation are done on chip The use of expensive ATE machines to test chips can be avoided. Requirements of a BIST scheme Easy to implement Small area overhead High fault coverage Advantage No need for expensive tester At-speed testing

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