1. CS 140L Lecture 6
Professor CK Cheng
5/05/02

2. Lab 3 Finite State Machine
Use State Diagram, ABEL layout (VHDL)
Mealy, Moore Machines
State Assignment
Project Manager.
New project: Family Spartan, Device S05PC84, Speed 4.
State Diagram (ABEL).
Create Macro Component.
Schematic Diagram: Call the component (Either on top or bottom of list).
Synthesis.
CLK
rst Z x
7. Timing Diagram.
8. Check Layout # CLBs
CLB

3. Transformation between Mealy and Moore Machines
Algorithm:
Given a state table with entries of NS, z
1) For each NS, z = Si,j create a state Si(j)
2) Replace NS, z (Si ,j) with state Si(j)
3) Set z = j if PS = Si(j)

4. Example Mealy Machine: Moore Machine: PS A B 00 A,0 A,1 01 A,1 B,0 10
(x,y)
B,0
B,1 (NS, z)
Moore Machine: PS A0 A1 B0 B1
(x,y) 00 A0 A1 01 A1 B0 10 A1 B0 11 B0 B1 z 1

5. Mealy State Diagram
00/0, 01/1, 10/1
10/0, 01/0, 11/1
11/0 B A
00/1

6. Moore State Diagram A0 A0 A0 A0 10 00 01 11 11 01 10 10 00 01 00 11 00

7. Timing Diagrams Time step x y S z A A0 1 A A0 2 1 A A1 3 1 B B0 4 1 BA A0 1 A A0 2 1 A A1 3 1 B B0 4 1 B B1 5 B 1 B0 6 1 A A1 7
B A 1
B0 A1
Mealy
Moore
(The output has a 1 clock shift between Mealy and Moore machines)