1. *
07/16/96
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Efficient Loop Handling for DSP algorithms on CISC, RISC and DSP processors
M. Smith,
Electrical and Computer Engineering,
University of Calgary, Alberta, Canada
ucalgary.ca *

2. To be tackled today Loop overhead -- depends on implementation
Performing multiple memory accesses to an array
Loop overhead can steal many cycles
Loop overhead -- depends on implementation
Standard loop with test at the start -- while ( )
Initial test with additional test at end -- do-while( )
Down-counting loops
Special Efficiencies
CISC -- hardware
RISC -- intelligent compilers
DSP -- hardware
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3. Review -- CISC processor instruction phases
Fetch -- Obtain op-code
PC-value out on Address Bus
Instruction op-code at Memory[PC] on Data Bus and then into Instruction Register
Decode -- Bringing required values (internal or external) to the ALU input.
Immediate -- Additional memory access for value -- Memory[PC]
Absolute -- Additional memory access for address value and then further access for value -- Memory[Memory[PC]]
Indirect -- Additional memory access to obtain value at Memory[AddressReg]
Execute -- ALU operation
Writeback -- ALU value to internal/external storage
May require additional memory accesses to obtain address used during storage
May require additional memory operations to perform storage.
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4. Clements -- Microprocessor Systems Design PWS Publishing ISBN 0-534-94822-7
Data from the memory
appears near the end of
the read cycle
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5. Access of cosine table -- Common DSP issue*
07/16/96
Need to access the cosine table during FFT, DCT etc
Calculation of cosines very time consuming
Pre-calculate and store. Overhead only access time
Simple increment -- cos[q] -- q = 0, k, 2k, 3k, 4k
Cosine values repeat every N
No need to store cosine values from N+ 1 to 2N
If 0 <= q < N then use CosineTable[q];
else N <= q < 2N then use CosineTable[q - N];
else 2N <= q < 3N then etc
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6. Similar problems when doing delay lines, FIR or IIR filters
Output pt
Input pt A2
A11
Output pt
Input pt A3
A12
Output pt
Input pt
A13 A4
Input pt
Output pt
A14 A5
Similar problems when doing delay lines, FIR or IIR filters
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7. CISC -- Accessing arrays when indexing is not simple
cos[q] -- q = 0, k, 2k, 3k, 4k -- 68K bit CISC
start with #define c_address &cos[0] MOVEA.L #x_address, A FETCH (4) LOAD (2 * 4) STORE (0)
loop handling
for (loop = 0, loop < (n- 1) k; loop += k
// put cos value in D MOVE.L (A0), D FETCH (4) LOAD (2 * 4) STORE (0) ADD.L #(4 *k), A FETCH (4) LOAD (2 * 4) STORE (0) ADD32 (4?)
endfor
Problems -- k is a constant -- unnecessary extra cycles
Pointer A2 can get beyond end of fixed ROM array -- tackle next lecture
Code from actual loop itself takes time
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8. Timing required to handle DSP loops
for k = 0 to (N-1) Body of Code -- BofC cycles
endfor
Important feature -- how much overhead time is used in handling the loop construct itself?
Three components
Set up Time
Body of code time -- BofC cycles
Handling the loop itself
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9. Basic Loop body Set up loop -- loop overhead -- done once
Check conditions -- loop overhead -- done many times
Do Code Body -- done many times -- useful
Loop Back + counter increment loop overhead -- many
Define Loop Efficiency = N * Tcodebody Tsetup + N * (Tcodebody + Tconditions + Tloopback)
Different Efficiencies depending on size of the loop
Need to learn good approximation techniques and recognize the two extremes
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10. 3 basic loop constructs While loop
Main compare test at top of loop
Modified do-while loop with initial test
Initial compare test at top
Main compare test at the bottom of the loop
Down-counting do-while loop with initial test
No compare operations in test.
Relies on the setting of condition code flags during adjustment of the loop counter.
Can increase overhead in some algorithms
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11. Basic 68K CISC loop -- Test at start
MOVE.L #0, count -- Set up -- count in register Fetch instr. (FI4) + Fetch 32-bit constant (FC 2 * 4) + operation (OP0)
LOOP: CMP.L #N, count -- (FI4 FC8, OP bit subtract) BGE somewhere Actually ADD.L #(somewhere - 4), PC (ADD OF 16-bit DISPLACEMENT TO PC -- FI4 FC4 OP(0 or 4) )
Body Cycles
ADD.L #1, count -- (FI4, FC8, OP4) JMP LOOP (FI4, FC8, OP4)
N * BodyCycles LOOP EFFECIENCY = N*(28 + BodyCycles + 32)
Since 60 >> 12 (5 times) then ignore startup cycles even if N small
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12. Check at end -- 68K CISC loop
MOVE.L #0, count (FI4, FC8, OP0) JMP LOOPTEST (FI4, FC8, OP4)
LOOP: Body Cycles
ADD.L #1, count (FI4, FC8, OP4)
LOOPTEST: CMP.L #N, count -- (FI4, FC8, OP4) BLT LOOP (FI4, FC4, OP4)
N * BodyCycles EFFECIENCY = N*BodyCycles + 44*(N+1)
Since 44 > 26 (1.8 times) then can’t Ignore startup cycles if N small and Body Cycles small -- Small loop means inefficient
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13. Down Count -- 68K CISC loop
MOVEQ.L #0, array_index -- (FI4, FC0, OP0) MOVE.L #N, count (FI4, FC0, OP0) JMP LOOPTEST (FI4, FC8, OP4)
LOOP:
BodyCycles using instructions of form OPERATION (Addreg, Index)
ADDQ.L #1, array_index -- (FI4, FC0, OP0?)
SUBQ.L #1, count (FI4, FC0, OP0?)
LOOPTEST : BGT LOOP (FI4, FC4, OP4)
N * BodyCycles Loop Efficiency = N*BodyCycles + 20*(N+1)
Since 20 < 24 then can’t Ignore startup if N small and Body Cycles small
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14. Down Count -- Possible sometimes
MOVEA.L #array_start, Addreg -- (FI4, FC0, OP0) MOVE.L #N, count (FI4, FC0, OP0) JMP LOOPTEST (FI4, FC8, OP4)
LOOP:
BodyCycles using autoincrement mode OPCODE (Addreg)+
SUBQ.L #1, count (FI4, FC0, OP0?)
LOOPTEST : BGT LOOP (FI4, FC4, OP4)
N * BodyCycles Loop Efficiency = N*BodyCycles + 16*(N+1)
Since 16 < 24 then can’t Ignore startup if N small and Body Cycles small
NOTE -- Number of cycles needed in body of the loop decreases in this case
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15. Loop Efficiency on CISC processor
Efficiency depends on how loop constructed
Standard while-loop
Check at end -- modified do-while
Down counting -- with/without auto-incrementing addressing modes
Compiler versus hardcode efficiency
See Embedded System Design magazine Sept./Oct 2000
What happens with different processor architectures?
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16. Check at end -- 29K RISC loop
CONST count, (1 cycle) JUMP LOOPTEST (1 cycle) NOP (1 cycle -- delay slot)
LOOP:
Bodycycles -- autoincrementing mode -- NOT AN OPTION
ADDU count, count, (1 cycle)
LOOPTEST: CPLE TruthReg, count, N (1 cycle should be 2 -- register forwarding) (Boolean Truth Flag in TruthReg -- which could be any register) JMPT TruthReg LOOP (1 cycle) NOP (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = N * BodyCycles + 4*(N+1)
Since 4 = 3 then can’t Ignore startup if N small and Body Cycles small
Since dealing with single cycle operations -- body cycle count smaller
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17. Down Count -- 29K RISC loop
CONST index, cycle
JUMP LOOPTEST cycle CONST count, N in delay slot
LOOP:
BodyCycles
SUBU count, count, cycle
LOOPTEST: CPGT TruthReg, count, cycle JMPT TruthReg, LOOP cycle ADDS index, index, in delay N * BodyCycles Loop Efficiency = N*BodyCycles + 4*(N+1)
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18. Efficiency on RISC processors
Not much difference between
Test at end, Down count loop format
HOWEVER body-cycle count has decreased
Processor is highly pipelined -- Loop jumps cause the pipeline to stall
Need to take advantage of delay slots
Efficiency depends on DSP algorithm being implemented?
What about DSP processors?
Architecture is designed for efficiency in this area.
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19. Check at end -- ADSP-21K loop
count, = 0; (1 cycle) number = N; (1 cycle) JUMP LOOPTEST (DB); (1 cycle) NOP; (1 cycle -- delay slot) NOP; (1 cycle -- delay slot)
LOOP:
BODYCYCLES
count = count + 1; (1 cycle)
LOOPTEST Comp(count, number); -- (1 cycle) IF LT JUMP LOOP (DB); (1 cycle) NOP; (1 cycle -- delay slot) NOP; (1 cycle -- delay slot) N * BodyCycles EFFICIENCY = N*BodyCycles + 5*(N+1)
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20. Speed improve -- Possible?
count = 1; (1 cycle) number = N; (1 cycle) JUMP LOOPTEST (DB); (1 cycle) count = count - 1; (1 cycle -- delay slot) number = number - 1; (1 cycle -- delay slot)
LOOP:
BODYCYCLES
count = count + 1; (1 cycle)
LOOPTEST Comp(count, number); -- (1 cycle) IF LT JUMP LOOP (DB); (1 cycle) count = count + 1; (1 cycle -- delay slot) NOP; (1 cycle -- delay slot) N * BodyCycles EFFICIENCY = N*BodyCycles + 4*(N+1)
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21. Down Count -- ADSP-21K loop
number = 0; (1 cycle) JUMP (PC, LOOPTEST) (DB); (1 cycle) index = 0; (1 cycle -- in delay slot) count = N ; (1 cycle -- in delay slot)
LOOP: Bodycycles
count = count - 1; (1 cycle)
LOOPTEST Comp(count, number); -- (1 cycle) IF GT JUMP (PC, LOOP) (DB); (1 cycle) index = index + 1; (1 cycle -- delay slot) NOP; (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = N*BodyCycles + 5*(N+1)
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22. *
Improved Down Count -- ADSP21K loop Is code valid -- or 1 off in times around loop?
07/16/96
number = -1; Bias the loop counter (1 cycle) JUMP (PC, LOOPTEST) (DB); (1 cycle) index = 0; (1 cycle -- in delay slot) count = (N-1); (1 cycle -- in delay slot)
LOOP: Body cycles
LOOPTEST Comp(count, number); -- (1 cycle) IF GT JUMP (PC, LOOP); (1 cycle) index = index + 1; (1 cycle -- delay slot) count = count - 1; (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = N*BodyCycles + 4*(N+1)
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23. Faster Loops Need to go to special features
CISC -- special Test, Conditional Jump and Decrement in 1 instruction
RISC -- Change algorithm format
DSP -- Special hardware for loops
Maximum of six-nested loops
Can be a hidden trap when writing “C”
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24. Recap -- 68K CISC loop down count
MOVEQ.L #0, index (FI4, FC0, OP0) MOVE.L #N, count (FI4, FC0, OP0) JMP LOOPTEST (FI4, FC8, OP4)
LOOP:
BodyCycles
ADDQ.L #1, index (FI4, FC0, OP0?)
SUBQ.L #1, count (FI4, FC0, OP0?)
LOOPTEST : BGT LOOP (FI4, FC4, OP4)
N * BodyCycles Loop Efficiency = N*BodyCycles + 20*(N+1)
Since 24=20 then can’t Ignore startup if N small and Body Cycles small
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25. Hardware 68K CISC loop
MOVEQ.L #0, index (FI4 FC0 OP0) MOVE.L #(N-1), count (FI4 FC0 OP0) JMP LOOPTEST (FI4, FC8, OP4)
LOOP:
BodyCycles
ADDQ.L #1, index (FI4, FC0 OP0?)
LOOPTEST: DBCC count, LOOP (FI4, FC4, OP4)
N * BodyCycles Loop Efficiency =
24 + N*BodyCycles + 16*(N+1)
Possibility that Efficiency almost 100% if the Body Instructions are small enough to fit into cache
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26. Custom loop hardware on RISC
For long loops -- loop overhead small -- no need to be concerned about the loop overhead (unless loop in loop)
For small loops -- unroll the loop so that hardcoded
20 instructions rather than 1 instruction looped 20 times
For medium loops -- advantage over CISC normally is that instructions more efficient -- 1 cycles compared to cycles
For medium loops -- advantage over DSP normally is that instructions more efficient
1 RISC cycle compared to 2 DSP cycles -- (not 21K since 1 to 1)
For more information
See the Micro 1992 articles
See the CCI articles
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27. 21k Processor architecture
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28. DAG generator architecture
Animation from SHARCNavigator on diskette from office
Also see DSP workshop book and exercises
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29. Recap -- Improved Down Count -- 21K DSP loop*
07/16/96
number = (1 cycle) JUMP (PC, LOOPTEST) (DB) (1 cycle) index = (1 cycle -- in delay slot) count = (N-1) (1 cycle -- in delay slot)
LOOP: Body cycles
LOOPTEST Comp(count, number) -- (1 cycle ) IF GT JUMP (PC, LOOP) (1 cycle) index = index (1 cycle -- delay slot) count = count (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = N*BodyCycles + 4*(N+1)
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30. Hardware Loop -- 21K DSP loop
count = N (1 cycle)
count = pass count (1 cycle) IF LE JUMP (PC, PASTLOOP) (DB) -- (1 cycle) index = (1 cycle -- in delay slot) nop (1 cycle -- in delay slot)
HARDWARE_LOOP: LCNTR N; do PASTLOOP-1 until LCE cycle -- parallel instruction Body-cycles
PASTLOOP: Last cycle of loop is at location PASTLOOP -1
Rest of the program code N * BodyCycles Loop Efficiency = N*BodyCycles)
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31. DSP Hardware loop Efficiency from a number of areas Hardware counter
No overhead for decrement
No overhead for compare
Pipelining efficient
Processor knows to fetch instructions from start of loop, not past the loop
Has some problems if loop size is too small -- loop timing is longer than expected as processor needs to flush the pipeline and restart it
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32. Tackled today Loop overhead -- depends on implementation
Performing access to memory in a loop
Loop overhead can steal many cycles
Loop overhead -- depends on implementation
Standard loop with test at the start -- while ( )
Initial test with additional test at end -- do-while( )
Down-counting loops
Special Efficiencies
CISC -- hardware
RISC -- intelligent compilers
DSP -- hardware
1/2/2019
ENCM High Speed Loops -- Hardware and Software
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