1. CSE 140L Discussion 3 CK Cheng and Thomas Weng
4-bit adder, multiplexer, timing diagrams, propagation delays

2. Timing behavior Real circuits have delays
Gate delay – time it takes for an output of the gate to change after its input changes
We can simulate timing delays in Quartus II to see these delays

3. Gate delay Notice rise time, fall time, and gate delay: input output

4. Quartus II Timing Simulation
Notice the delay in the output

5. 4-bit Ripple Carry Adders
Chain 4 1-bit full adders together, and connect the carry out of the previous adder with the carry in of the next adder.
Delay path: critical path from A0, B0, or C0 to S3, C4

6. Critical Path for worst delay
Propagation from C0 to C4
C4 changes as C0 toggles C0
1110
0001 C4

7. Multiplexers
-Multiplexers (MUXes) are like selectors. There is one output, 2 or more inputs, and a “selector” input that determines which of those inputs gets outputed.
-Allows several devices to share one single line.
This is a 2:1 mux. It has 2 inputs, 1 output. Because there are only 2 inputs, S is one bit. If S=0, then we output A. If S=1, then we output B. A
MUX Z B S

8. Multiplexers -Here is the truth table for the 1-bit 2:1 MUX.Z 1
When S is 0, the MUX will select whatever A is. If A is 1, then the MUX will output 1. It doesn’t matter what B is. When S is 1, then the MUX will output whatever B is.
The boolean equation can be written as:
Z = (A S) + (B S)

9. Multiplexers -MUX can be implemented very simply.
-The two AND gates determine which of the two inputs goes through. If S is 0, then I0 will be ANDed with a 1, so that goes through. I1 will be ANDed with a 0, and thus won’t go through.

10. Multiplexers -We can also make a 4:1 MUX using three 2:1 MUX
If S1S0 = 00, then S1 will select MUX from A and B. Since S0=0. Z= A. A
MUX B 1
MUX Z S0 Z 1 C
MUX S1 D 1

11. Multiplexers -We can make 4:1 and above MUXes too.
-With 4 inputs, our selector needs to have two bits.