1. Chapter 3 – Combinational Logic Design
Logic Circuit Design
Chapter 3 – Combinational Logic Design

2. Overview Part 1 – Design Procedure Overview Steps
Specification
Formulation
Optimization
Technology Mapping
Beginning Hierarchical Design
Technology Mapping - AND, OR, and NOT to NAND or NOR
Verification
Manual
Simulation

3. Overview (continue) Part 2 – Combinational Logic Overview
Functions and functional blocks
Rudimentary logic functions
Decoding using Decoders
Implementing Combinational Functions with Decoders
Encoding using Encoders
Selecting using Multiplexers
Implementing Combinational Functions with Multiplexers

4. 3-1 Beginning Hierarchical Design
Combinational Circuits
A combinational logic circuit has:
A set of m Boolean inputs,
A set of n Boolean outputs, and
n switching functions, each mapping the 2m input combinations to an output such that the current output depends only on the current input values
A block diagram:
m Boolean Inputs
n Boolean Outputs
Combinatorial
Logic
Circuit

5. 3-1 Beginning Hierarchical Design
Design Procedure
Specification
Write a specification for the circuit if one is not already available
Formulation
Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification
Apply hierarchical design if appropriate
Optimization
Apply 2-level and multiple-level optimization
Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters

6. 3-1 Beginning Hierarchical Design
Design Procedure
Technology Mapping
Map the logic diagram or netlist to the implementation technology selected
Verification
Verify the correctness of the final design manually or using simulation

7. 3-1 Beginning Hierarchical Design
Design Example
Specification
4-Bit equality Comparator
Compares two binary vectors to determine whether they are equal or not
Inputs consist of tow vectors: A(3:0) and B(3:0)
Output is a single-bit variable E
A and B are equal then E=1
A and B are unequal then E=0

8. 3-1 Beginning Hierarchical Design
Design Example (continue)
Formulation

9. 3-1 Beginning Hierarchical Design
Design Example (continue)
3. Optimization
𝑁 𝑖 = 𝐴 𝑖 𝐵 𝑖 + 𝐴 𝑖 𝐵 𝑖
𝐸= 𝑁 0 + 𝑁 1 + 𝑁 2 + 𝑁 3

10. 3-1 Beginning Hierarchical Design
To control the complexity of the function mapping inputs to outputs:
Decompose the function into smaller pieces called blocks
Decompose each block’s function into smaller blocks, repeating as necessary until all blocks are small enough
Any block not decomposed is called a primitive block
The collection of all blocks including the decomposed ones is a hierarchy

11. 3-1 Beginning Hierarchical Design
Reusable Functions
Whenever possible, we try to decompose a complex design into common, reusable function blocks
These blocks are
verified and well-documented
placed in libraries for future use

12. 3-1 Beginning Hierarchical Design
Hierarchy

13. 3-1 Beginning Hierarchical Design
Top-Down versus Bottom-Up
A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement
A bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks
Design usually proceeds top-down to known building blocks ranging from complete CPUs to primitive logic gates or electronic components.
Much of the material in this chapter is devoted to learning about combinational blocks used in top-down design.

14. Technology Mapping Mapping Procedures 3-2 Technology Mapping
To NAND gates
To NOR gates
Mapping to multiple types of logic blocks in covered in the reading supplement: Advanced Technology Mapping.

15. Mapping to NAND gates 3-2 Technology Mapping Assumptions:
Gate loading and delay are ignored
Cell library contains an inverter and n-input NAND gates, n = 2, 3, …
An AND, OR, inverter schematic for the circuit is available
The mapping is accomplished by:
Replacing AND and OR symbols,
Pushing inverters through circuit fan-out points, and
Canceling inverter pairs

16. NAND Mapping Algorithm
3-2 Technology Mapping
NAND Mapping Algorithm
Replace ANDs and ORs:
Repeat the following pair of actions until there is at most one inverter between :
A circuit input or driving NAND gate output, and
The attached NAND gate inputs.

17. Ex. 3-2 Implementation with NAND gates
3-2 Technology Mapping
Ex. 3-2 Implementation with NAND gates
𝐹=𝐴𝐵+ (𝐴𝐵) 𝐶+ (𝐴𝐵) 𝐷 +𝐸

18. Mapping to NOR gates 3-2 Technology Mapping Assumptions:
Gate loading and delay are ignored
Cell library contains an inverter and n-input NOR gates, n = 2, 3, …
An AND, OR, inverter schematic for the circuit is available
The mapping is accomplished by:
Replacing AND and OR symbols,
Pushing inverters through circuit fan-out points, and
Canceling inverter pairs

19. NOR Mapping Algorithm Replace ANDs and ORs:
3-2 Technology Mapping
NOR Mapping Algorithm
Replace ANDs and ORs:
Repeat the following pair of actions until there is at most one inverter between :
A circuit input or driving NOR gate output, and
The attached NOR gate inputs.

20. Ex. 3-3 Implementation with NOR gates
3-2 Technology Mapping
Ex. 3-3 Implementation with NOR gates
𝐹=𝐴𝐵+ (𝐴𝐵) 𝐶+ (𝐴𝐵) 𝐷 +𝐸

21. 3-2 Technology Mapping
Verification
Verification - show that the final circuit designed implements the original specification
Simple specifications are:
truth tables
Boolean equations
HDL code
If the above result from formulation and are not the original specification, it is critical that the formulation process be flawless for the verification to be valid!

22. Basic Verification Methods
3-2 Technology Mapping
Basic Verification Methods
Manual Logic Analysis
Find the truth table or Boolean equations for the final circuit
Compare the final circuit truth table with the specified truth table, or
Show that the Boolean equations for the final circuit are equal to the specified Boolean equations
Simulation
Simulate the final circuit (or its netlist, possibly written as an HDL) and the specified truth table, equations, or HDL description using test input values that fully validate correctness.
The obvious test for a combinational circuit is application of all possible “care” input combinations from the specification

23. 3-3 Combinational Functional Blocks
Functions and Functional Blocks
The functions considered are those found to be very useful in design
Corresponding to each of the functions is a combinational circuit implementation called a functional block.
In the past, functional blocks were packaged as small- scale-integrated (SSI), medium-scale integrated (MSI), and large-scale-integrated (LSI) circuits.
Today, they are often simply implemented within a very- large-scale-integrated (VLSI) circuit.

24. 3-3 Combinational Functional Blocks
Block Diagram of a Sequential Circuit

25. 3-4 Rudimentary Logic Functions
Value-Fixing, Transferring, and Inverting
Functions of a single variable X
Can be used on the inputs to functional blocks to implement other than the block’s intended function

26. 3-4 Rudimentary Logic Functions
Multiple-Bit Function
Multi-bit Examples:
A wide line is used to represent a bus which is a vector signal
In (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)
Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.
The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F.

27. 3-4 Rudimentary Logic Functions
Enabling Function
Enabling permits an input signal to pass through to an output
Disabling blocks an input signal from passing through to an output, replacing it with a fixed value
The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1
When disabled, 0 output (a)
When disabled, 1 output (b)
See Enabling App in text

28. 3-5 Decoding
Decoding
Decoding - the conversion of an n-bit input code to an m- bit output code with n £ m £ 2n such that each valid code word produces a unique output code
Circuits that perform decoding are called decoders
Here, functional blocks for decoding are
called n-to-m line decoders, where m £ 2n, and
generate 2n (or fewer) minterms for the n input variables

29. 3-5 Decoding
Decoder Examples
1-to-2-Line Decoder
2-to-4-Line Decoder
Note that the 2-4-line made up of 2 1-to-2- line decoders and 4 AND gates.

30. Decoder Expansion 3-5 Decoding
General procedure given in book for any decoder with n inputs and 2n outputs.
This procedure builds a decoder backward from the outputs.
The output AND gates are driven by two decoders with their numbers of inputs either equal or differing by 1.
These decoders are then designed using the same procedure until 2-to-1-line decoders are reached.
The procedure can be modified to apply to decoders with the number of outputs ≠ 2n

31. Decoder Expansion – Example 1
3-5 Decoding
Decoder Expansion – Example 1
3-to-8-line decoder
Number of output ANDs = 8
Number of inputs to decoders driving output ANDs = 3
Closest possible split to equal
2-to-4-line decoder
1-to-2-line decoder
Number of output ANDs = 4
Number of inputs to decoders driving output ANDs = 2
Two 1-to-2-line decoders
See next slide for result

32. Decoder Expansion – Example 1
3-5 Decoding
Decoder Expansion – Example 1
Result

33. Decoder Expansion – Example 2
3-5 Decoding
Decoder Expansion – Example 2
6-to-64 -line decoder

34. Decoder with Enable 3-5 Decoding
In general, attach m-enabling circuits to the outputs
See truth table below for function
Note use of X’s to denote both 0 and 1
Combination containing two X’s represent four binary combinations
Alternatively, can be viewed as distributing value of signal EN to 1 of 4 outputs
In this case, called a demultiplexer

35. Combinational Logic Implementation - Decoder and OR Gates
3-5 Decoding
Combinational Logic Implementation - Decoder and OR Gates
Implement m functions of n variables with:
Sum-of-minterms expressions
One n-to-2n-line decoder
m OR gates, one for each output
Approach 1:
Find the truth table for the functions
Make a connection to the corresponding OR from the corresponding decoder output wherever a 1 appears in the truth table
Approach 2
Find the minterms for each output function
OR the minterms together

36. Decoder and OR Gates Example
3-5 Decoding
Decoder and OR Gates Example
𝑆= 𝑚 1, 2, 4, 𝐶= 𝑚 (3, 5,6,7)

37. 3-6 Encoding
Encoding
Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n £ m £ 2n such that each valid code word produces a unique output code
Circuits that perform encoding are called encoders
An encoder has 2n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values
Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.

38. Encoder Example A decimal-to-BCD encoder
3-6 Encoding
Encoder Example
A decimal-to-BCD encoder
Inputs: 10 bits corresponding to decimal digits 0 through 9, (D0, …, D9)
Outputs: 4 bits with BCD codes
Function: If input bit Di is a 1, then the output (A3, A2, A1, A0) is the BCD code for i,
The truth table could be formed, but alternatively, the equations for each of the four outputs can be obtained directly.

39. Encoder Example (continued)
3-6 Encoding
Encoder Example (continued)
Input Di is a term in equation Aj if bit Aj is 1 in the binary value for i.
Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
F1 = D6 + D7 can be extracted from A2 and A1 Is there any cost saving?

40. 3-6 Encoding
Priority Encoder
If more than one input value is 1, then the encoder just designed does not work.
One encoder that can accept all possible combinations of input values and produce a meaningful result is a priority encoder.
Among the 1s that appear, it selects the most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position.

41. Priority Encoder Example
3-6 Encoding
Priority Encoder Example

42. Priority Encoder Example (continue)
3-6 Encoding
Priority Encoder Example (continue)

43. Priority Encoder Example (continue)
3-6 Encoding
Priority Encoder Example (continue)

44. 3-7 Selecting
Selecting
Selecting of data or information is a critical function in digital systems and computers
Circuits that perform selecting have:
A set of information inputs from which the selection is made
A single output
A set of control lines for making the selection
Logic circuits that perform selecting are called multiplexers
Selecting can also be done by three-state logic or transmission gates

45. 2-to-1-Line Multiplexer
3-7 Selecting
2-to-1-Line Multiplexer
Since 2 = 21, n = 1
The single selection variable S has two values:
S = 0 selects input I0
S = 1 selects input I1
The equation:
𝑌= 𝑆 𝐼 0 +𝑆 𝐼 1

46. 2-to-1-Line Multiplexer (continue)
3-7 Selecting
2-to-1-Line Multiplexer (continue)

47. 4-to-1-Line Multiplexer
3-7 Selecting
4-to-1-Line Multiplexer

48. Multiplexer Width Expansion
3-7 Selecting
Multiplexer Width Expansion
Select “vectors of bits” instead of “bits”
Use multiple copies of 2n ´ 2 AND-OR in parallel
Example: quad 4-to-1- line multiplexer

49. Combinational Logic Implementation - Multiplexer Approach 1
3-7 Selecting
Combinational Logic Implementation - Multiplexer Approach 1
Implement m functions of n variables with:
Sum-of-minterms expressions
An m-wide 2n-to-1-line multiplexer
Design:
Find the truth table for the functions.
In the order they appear in the truth table:
Apply the function input variables to the multiplexer inputs Sn - 1, … , S0
Label the outputs of the multiplexer with the output variables
Value-fix the information inputs to the multiplexer using the values from the truth table (for don’t cares, apply either 0 or 1)

50. Example: Gray to Binary Code
3-7 Selecting
Example: Gray to Binary Code
Design a circuit to convert a 3-bit Gray code to a binary code
The formulation gives the truth table on the right
It is obvious from this table that X = C and the Y and Z are more complex
Gray
A B C
Binary
x y z
1 0
0 1 1
0 1 0
1 0 1

51. Example: Gray to Binary Code (continued)
3-7 Selecting
Example: Gray to Binary Code (continued)
Rearrange the table so that the input combinations are in counting order
Functions y and z can be implemented using a dual 8-to-1-line multiplexer by:
connecting A, B, and C to the multiplexer select inputs
placing y and z on the two multiplexer outputs
connecting their respective truth table values to the inputs

52. Example: Gray to Binary Code (continued)
3-7 Selecting
Example: Gray to Binary Code (continued)
Note that the multiplexer with fixed inputs is identical to a ROM with 3-bit addresses and 2-bit data!
D00
D10 1 1
D01
D11 1 1
D02
D12
D03
D13
D04 1
D14
Out Y
Out Z 1
D05
D15 1
D06
D16 1
D07
D17 A S2 A S2
8-to-1
8-to-1 B S1 B S1
MUX
MUX S0 S0 C C

53. Combinational Logic Implementation - Multiplexer Approach 2
3-7 Selecting
Combinational Logic Implementation - Multiplexer Approach 2
Implement any m functions of n + 1 variables by using:
An m-wide 2n-to-1-line multiplexer
A single inverter
Design:
Find the truth table for the functions.
Based on the values of the first n variables, separate the truth table rows into pairs
For each pair and output, define a rudimentary function of the final variable (0, 1, 𝑋, 𝑋 )
Using the first n variables as the index, value-fix the information inputs to the multiplexer with the corresponding rudimentary functions
Use the inverter to generate the rudimentary function 𝑋

54. Example: Gray to Binary Code
3-7 Selecting
Example: Gray to Binary Code
Design a circuit to convert a 3-bit Gray code to a binary code
The formulation gives the truth table on the right
It is obvious from this table that X = C and the Y and Z are more complex
Gray
A B C
Binary
x y z
1 0
0 1 1
0 1 0
1 0 1

55. Rudimentary Functions of C for z
3-7 Selecting
Example: Gray to Binary Code (continued)
Rearrange the table so that the input combinations are in counting order, pair rows, and find rudimentary functions
Gray
A B C
Binary
x y z
Rudimentary
Functions of C for y
Rudimentary Functions of C for z
0 0 0
0 0 1
1 1 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
F = C
F = C
F = C
F = C
F = C
F = C
F = C
F = C

56. Example: Gray to Binary Code (continued)
3-7 Selecting
Example: Gray to Binary Code (continued)
Assign the variables and functions to the multiplexer inputs:
Note that this approach (Approach 2) reduces the cost by almost half compared to Approach 1.
This result is no longer ROM-like
Extending, a function of more than n variables is decomposed into several sub- functions defined on a subset of the variables. The multiplexer then selects among these sub-functions. S1 S0 A B
D03
D02
D01
D00
Out Y
8-to-1
MUX C
D13
D12
D11
D10 Z

57. 3-9 Binary Adders
Half Adder

58. 3-9 Binary Adders
Full Adder

59. Full Adder (continued)
3-9 Binary Adders
Full Adder (continued)

60. Binary Ripple Carry Adder
3-9 Binary Adders
Binary Ripple Carry Adder

61. Unsigned Subtraction Algorithm: Examples: 3-10 Binary Subtraction
Subtract the subtrahend N from the minuend M
If no end borrow occurs, then M ³ N, and the result is a non- negative number and correct.
If an end borrow occurs, the N > M and the difference M - N + 2n is subtracted from 2n, and a minus sign is appended to the result.
Examples:
(-)

62. Unsigned Subtraction (continued)
3-10 Binary Subtraction
Unsigned Subtraction (continued)
The subtraction, 2n - N, is taking the 2’s complement of N
To do both unsigned addition and unsigned subtraction requires:
Quite complex!
Goal: Shared simpler logic for both addition and subtraction
Introduce complements as an approach

63. Complements Two complements:
3-10 Binary Subtraction
Complements
Two complements:
Diminished Radix Complement of N
(r - 1)’s complement for radix r
1’s complement for radix 2
Defined as (rn - 1) - N
Radix Complement
r’s complement for radix r
2’s complement in binary
Defined as rn - N
Subtraction is done by adding the complement of the subtrahend
If the result is negative, takes its 2’s complement

64. Binary 1's Complements For r = 2, N = 011100112, n = 8 (8 digits):
3-10 Binary Subtraction
Binary 1's Complements
For r = 2, N = , n = 8 (8 digits):
(rn – 1) = = or
The 1's complement of is then: –
Since the 2n – 1 factor consists of all 1's and since 1 – 0 = 1 and 1 – 1 = 0, the one's complement is obtained by complementing each individual bit (bitwise NOT).

65. 3-10 Binary Subtraction
Binary 2's Complements
For r = 2, N = , n = 8 (8 digits), we have:
(rn ) = or
The 2's complement of is then: –
Note the result is the 1's complement plus 1, a fact that can be used in designing hardware

66. Alternate 2’s Complement Method
3-10 Binary Subtraction
Alternate 2’s Complement Method
Given: an n-bit binary number, beginning at the least significant bit and proceeding upward:
Copy all least significant 0’s
Copy the first 1
Complement all bits thereafter.
2’s Complement Example:
Copy underlined bits:
100
and complement bits to the left:

67. Subtraction with 2’s Complement
3-10 Binary Subtraction
Subtraction with 2’s Complement
For n-digit, unsigned numbers M and N, find M  N in base 2:
Add the 2's complement of the subtrahend N to the minuend M: M + (2n  N) = M  N + 2n
If M  N, the sum produces end carry rn which is discarded; from above, M - N remains.
If M < N, the sum does not produce an end carry and, from above, is equal to 2n  ( N  M ), the 2's complement of ( N  M ).
To obtain the result  (N – M) , take the 2's complement of the sum and place a  to its left.

68. 3-10 Binary Subtraction
Example 1
Find – –
The carry of 0 indicates that a correction of the result is required.
Result = – ( )
2’s comp
2’s comp

69. 3-11 Binary Adder-Subtraction
Signed Integers
Positive numbers and zero can be represented by unsigned n- digit, radix r numbers. We need a representation for negative numbers.
To represent a sign (+ or –) we need exactly one more bit of information (1 binary digit gives 21 = 2 elements which is exactly what is needed).
Since computers use binary numbers, by convention, the most significant bit is interpreted as a sign bit:
s an–2  a2a1a0 where: s = 0 for Positive numbers s = 1 for Negative numbers and ai = 0 or 1 represent the magnitude in some form.

70. 3-11 Binary Adder-Subtraction
Signed Integers Representations
Signed-Magnitude – here the n – 1 digits are interpreted as a positive magnitude.
Signed-Complement – here the digits are interpreted as the rest of the complement of the number. There are two possibilities here:
Signed 1's Complement
Uses 1's Complement Arithmetic
Signed 2's Complement
Uses 2's Complement Arithmetic

71. 3-11 Binary Adder-Subtraction
Signed Integers Representations Example
r =2, n=3
Number
Sign -
Mag.
1's Comp.
2's Comp. +3
011 +2
010 +1
001 +0
000 –
100
111 — 1
101
110 2 3 4

72. 3-11 Binary Adder-Subtraction
Signed-Magnitude Arithmetic
If the parity of the three signs is 0:
1. Add the magnitudes.
2. Check for overflow (a carry out of the MSB)
3. The sign of the result is the same as the sign of the first operand.
If the parity of the three signs is 1:
1. Subtract the second magnitude from the first.
2. If a borrow occurs:
take the two’s complement of result
and make the result sign the complement of the sign of the first operand.
3. Overflow will never occur.

73. 3-11 Binary Adder-Subtraction
Signed-Complement Arithmetic
Addition:
1. Add the numbers including the sign bits, discarding a carry out of the sign bits (2's Complement), or using an end- around carry (1's Complement).
2. If the sign bits were the same for both numbers and the sign of the result is different, an overflow has occurred.
3. The sign of the result is computed in step 1.
Subtraction:
Form the complement of the number you are subtracting and follow the rules for addition.

74. 3-11 Binary Adder-Subtraction
Overflow Detection
Overflow occurs if n + 1 bits are required to contain the result from an n-bit addition or subtraction
Overflow can occur for:
Addition of two operands with the same sign
Subtraction of operands with different signs
Signed number overflow cases with correct result sign
Detection can be performed by examining the result signs which should match the signs of the top operand

75. 3-12 Other Arithmetic Functions
Convenient to design the functional blocks by contraction - removal of redundancy from circuit to which input fixing has been applied
Functions
Incrementing
Decrementing
Multiplication by Constant
Division by Constant
Zero Fill and Extension

76. 3-12 Other Arithmetic Functions
Design by Contraction
Contraction is a technique for simplifying the logic in a functional block to implement a different function
The new function must be realizable from the original function by applying rudimentary functions to its inputs
Contraction is treated here only for application of 0s and 1s (not for X and 𝑋 )
After application of 0s and 1s, equations or the logic diagram are simplified by using rules given on pages of the text.

77. 3-12 Other Arithmetic Functions
Design by Contraction Example
Contraction of a ripple carry adder to incrementer for n = 3
Set B = 001
The middle cell can be repeated to make an incrementer with n > 3.

78. 3-12 Other Arithmetic Functions
Incrementing & Decrementing
Incrementing
Adding a fixed value to an arithmetic variable
Fixed value is often 1, called counting (up)
Examples: A + 1, B + 4
Functional block is called incrementer
Decrementing
Subtracting a fixed value from an arithmetic variable
Fixed value is often 1, called counting (down)
Examples: A - 1, B - 4
Functional block is called decrementer

79. 3-12 Other Arithmetic Functions
Multiplication/Division by 2n
(a) Multiplication by 100
Shift left by 2
(b) Division by 100
Shift right by 2
Remainder preserved B 1 2 3 C 4 5
(a) B 1 2 3 C
(b)

80. 3-12 Other Arithmetic Functions
Multiplication by a Constant
Multiplication of B(3:0) by 101
See text Figure 513 (a) for contraction B B B B B B B B 3 2 1 3 2 1
4-bit Adder
Carry
output
Sum C C C C C C C 6 5 4 3 2 1

81. 3-12 Other Arithmetic Functions
Zero Fill
Zero fill - filling an m-bit operand with 0s to become an n-bit operand with n > m
Filling usually is applied to the MSB end of the operand, but can also be done on the LSB end
Example: filled to 16 bits
MSB end:
LSB end:

82. 3-12 Other Arithmetic Functions
Extension
Extension - increase in the number of bits at the MSB end of an operand by using a complement representation
Copies the MSB of the operand into the new positions
Positive operand example extended to 16 bits:
Negative operand example extended to 16 bits:

83. Homework Homework Read Text Chapter 4, pp. 213-301
Prepare Presentation
Problems 1, 8, 12, 16, 18, 28, 29, 37, 44, 46