1. CS 5204 Operating Systems Lecture 10
Godmar Back

2. Announcements This week: first milestone meeting
Sign up now
Reports due by 5pm today
Midterm will be handed back next Monday (Oct 31)
Might switch some presentations - will update reading list and send to affected presenters
Move up SFI (John) & Nooks (Hari)
CS 5204 Fall 2005
1/2/2019

3. Plan for Today End-to-End argument Review memory management
CS 5204 Fall 2005
1/2/2019

4. Layered Architectures
(horizontal component)
Layer k may interact with peer layer k only via protocols
(vertical component)
Layer k+1 interacts with layer k via interface
CS 5204 Fall 2005
1/2/2019

5. Layering and the E2E Argument
Physical
Datalink
Network
Transport
Session
Presentation
Application
In any system using layering, designer has a choice of where to place functionality
Unless design by committee
CS 5204 Fall 2005
1/2/2019

6. End-to-end argument
If correct & complete implementation requires help & knowledge only endpoints have, do not push the functionality down into lower layers
Corollary:
A layer should only implement functionality that is needed by all clients, and can be completely implemented within that layer.
CS 5204 Fall 2005
1/2/2019

7. E2E Examples Careful file transfer Security & Encryption
Error detection & correction
Causal message delivery
CS 5204 Fall 2005
1/2/2019

8. E2E (cont’d) Note that endpoint != application
Endpoint can also be a layer
How to identify the endpoints?
Reasons for violating E2E:
Performance
Cost
Software engineering/Code Reuse (?)
E2E is only a guiding principle, a type of “Occam’s Razor”
CS 5204 Fall 2005
1/2/2019

9. Review Memory Management
Logical Organization
Physical Organization
Protection
Paging
CS 5204 Fall 2005
1/2/2019

10. Logical Organization MAX_USER Stack Heap Data Code/Text  Local
 Dynamic
Heap
Data
 Global/Static
Code/Text
CS 5204 Fall 2005
1/2/2019

11. Compilation and Memory Layout
hello.decaf:
void main() {
Print(“Hello”); }
hello.o
Linker
Stack
Decaf Compiler
ELF executable:
hello.s:
tmp:
.asciz “Hello”;
Loader
data
hello\0
Heap
text
Data
Assembler
Code/Text
CS 5204 Fall 2005
1/2/2019

12. Quick Demo of /proc/*/maps
CS 5204 Fall 2005
1/2/2019

13. Linux IA32 3+1 Model 4GB Kernel Stack MAX_USER =3GB Heap Data
 Local
 Dynamic
Heap
Data
 Global/Static
Code/Text
CS 5204 Fall 2005
1/2/2019

14. Linux IA32 3+1 Model (MT) 4GB Kernel MAX_USER =3GB Heap Data Code/Text
Stack 1
 Local
Stack 2
 Dynamic
Heap
Data
 Global/Static
Code/Text
CS 5204 Fall 2005
1/2/2019

15. Virtual Address Space Management
Key resource is virtual addresses
Memory objects occupy continuous regions:
Stacks of kernel threads
Data segment
Shared libraries:
Data, bss, text
Subtract space taken up by kernel if necessary
64bit architectures where sizeof (void*) == 8 this is practically no longer an issue
But tough on 32bit architectures
CS 5204 Fall 2005
1/2/2019

16. Virtual to Physical Mapping
Virtual Memory
Addresses
Physical Memory
Addresses
MMU
Virt_max: 0…2^sizeof(void*)
Phys_max: 0…RAMsize
Page Table:
V → P
CS 5204 Fall 2005
1/2/2019

17. OS Tasks for Virtual Memory Mgnt
Predominant technology today: Paging
Older technique: segmentation
Must maintain & update permissions for each page (Protection)
Must maintain & update VirtPhys mappings
and adjust on context switch
Must manage physical frames
Detect usage & store content of unused frames to secondary storage
CS 5204 Fall 2005
1/2/2019

18. Protection Memory is associated with protection bits:
R – Read
W – Write
X – Execute
U – User – can it be accessed in user mode
Oddball X86: pages only have “W” write bit + U bit. Recent addition “NX” bit – “don’t execute”
Note: OS has full control over what a virtual address resolves to for a given process
Trap is caused if it doesn’t resolve to anything at the moment
Trap is caused if permissions don’t allow attempted action
CS 5204 Fall 2005
1/2/2019

19. Maintaining V  P Mappings
Note that V  P translation happens on every memory access
Caching needed  cache is called TLB (“translation lookaside buffer”)
What happens on a TLB miss?
TLB misses can be handled in software or hardware:
Software: special handler must look up mapping and restore it (MIPS, Alpha)
Hardware: (x86) must follow data structure layout in memory so MMU can read information from there to refill TLB
CS 5204 Fall 2005
1/2/2019

20. x86 Virtual Address Translation
Pre-PAE x86
Microsoft Technet [URL]
CS 5204 Fall 2005
1/2/2019

21. Linux Page Table Structure
PAE x86 shown:
from two-level to three-level translation scheme ( vs )
Source:
Mel Gorman: Understanding the Linux Virtual Memory Manager
Linux’s internal structures mimic what MMU expects
Ports to other architectures must emulate x86 page tables in Linux kernel
CS 5204 Fall 2005
1/2/2019

22. TLB & Context Switches Note that mappings are process-specific:
Virtual address in process A maps to a different page then address in process B – every process gets it own address space
Either tag TLB entries with process id (MIPS) or flush entire TLB on context switch (x86)
The subsequent TLB misses are what makes a context switch expensive.
CS 5204 Fall 2005
1/2/2019

23. Managing Physical Frames
Now memory is viewed as a resource
Must keep track of what’s free, what’s in use
Buddy allocator
Must keep track of what’s stored in pages that are in use
Consumers are memory objects
User process objects (stacks, data, text, …)
In-kernel ones (file system buffer caches, packet buffers, etc.)
Algorithms
Idea: monitor how pages are accessed, write least used ones to disk
LRU heuristics, page buffering
CS 5204 Fall 2005
1/2/2019

24. Summary Memory Management involves
Logical organization of address space
Physical organization of memory
Policies for protection (page-based, traditionally)
Policies for paging
CS 5204 Fall 2005
1/2/2019