1. It has 12 inputs and a dedicated clock input.
EP1210
EP1200 is a 40-pin device.
It has 12 inputs and a dedicated clock input.
It also has 24 I/O pins each of which can be programmed as inputs or outputs.
One I/O pin can also be used as a second clock input line.
It is partitioned into 2 symmetrical segments, each segment containing 14 macrocells.
Each segment is further divided into 4 blocks.

2. EP1210 Block Diagram

3. Both block1 and block2 contain 4 macrocells, and has 6 product terms.
EP1210
Both block1 and block2 contain 4 macrocells, and has 6 product terms.
Block3 also has 4 macrocells, has and 8 products.
Besides 2 of the macrocells share 4 product terms and other 2 share another set of 4 product terms.
Block 4 contains 2 macrocells each of which forms the sum of 8 product terms.
The two segments in EP1200 communicate over a series of buses.
Within each segment, 8 out of the 14 macrocells transmit their true and complemented outputs on a 16-bit local bus and also transfer their outputs to their respective I/O pins.

4. Global communication is done via a 48 bus.
EP1210
Global communication is done via a 48 bus.
It carries the true and complement values of the 12 dedicated inputs, and outputs of the 4 macrocells in block 3 of each segment.
Each EP1210 macrocell contains an AND-OR structure and programmable I/O block.
The AND array can be programmed to generate 4 to 16 product terms.
These product terms are ORed together and may be fed back to the other macrocells or to itself or via D flip flop.

5. EP1210 Macrocell

6. EP1210 Macrocell
Alternatively the output at I/O pin is fed back to the AND array or via D flip flop.
EP1210 contains 2 internal paths which are used to distribute clock and latch enable signals.
One path drives the enable inputs of the latches associated with I/O and dedicated input latches.
The other path provides clock signals to the D flip flops of the macrocells.
It has 3 EPROM cells to select one of 8 operating modes of the clock signals.

7. EP1210 Clock Signal Modes