1. Powerful High Density Solutions
Xilinx/Synplicity
Powerful High Density Solutions

2. The Synplicity Advantage
Fast Growing Synthesis Vendor
50% quarter-to-quarter growth
Fastest HDL Synthesis Compiler in the Market
Focused on FPGA/CPLD Synthesis
Over 1800 Installed Seats

3. The Xilinx/Synplicity Advantage
The Key to Success is a Strong, Committed Partnership!
Synplicity is Committed to Xilinx & Xilinx Users
Aggressive plan for Xilinx-specific features & new device support
Cooperative Engineering Agreement (Jan. 1998) for supporting high-density Xilinx design flows
Proprietary B.E.S.T. algorithms optimized for Xilinx devices

4. Synplicity Product Matrix
VHDL/
Verilog HDL synthesis tool
Synplify
Synplify-Lite
Xilinx-Specific
Version
Verilog
HDL
synthesis
tool
Starts at $5K Xilinx- specific w/o HDL Analyst
Generate
RTL &
gate-level
schematics
HDL Analyst
$4K

5. Consider Synplify & Xilinx
Enhanced Designer Productivity Through Xilinx-Specific Optimization
Produce the Highest Quality-of-Results
Optimizes across hierarchical boundaries
Conservation of design abstraction (B.E.S.T.)
Graphical Constraints Editor (SCOPE)
Xilinx-specific technology mapping
Designer Productivity
HDL Analyst
Intuitive use model, intelligent Synplify-Xilinx defaults

6. Technology Innovations Combined With Ease-of-Use
Synplify Delivers
Technology Innovations Combined With Ease-of-Use
Technology Innovations:
B.E.S.T.™ algorithms optimize across hierarchical boundaries
System level graphical timing constraint system- SCOPE™
Fast compile times for even the largest devices
Built-in timing analysis displayed through HDL Analyst
Unique Finite State Machine Compiler
Integration with popular simulators and Alliance implementation software
Batch & TCL support
Easy to learn and use
Cadence endorsement of Synplify based upon
technical evaluation of leading synthesis products

7. Comprehensive Tool Integration
Electronic System Design Automation Tools
Renoir, Summit
Users RTL
and Output Logic
comb: process (pres_state)
begin
case pres_state is
when S0 =
z <=‘0’;
next_state <= S0;
else
next_state <=
HDL Analyst
HDL Analysis
Synplify:
- Verilog & VHDL
Synthesis
Simulators
Cadence:
- Verilog-XL
- Leapfrog VHDL
Model Technology:
- ModelSim
Synthesis
Mapped Netlist
Verilog and VHDL
Xilinx Alliance Series Implementation Software
input [4:0] ReadRegSel;
input WriteReg;
output [15:0] RegData;
ram32x16 RAM_BLOCK ( .Q(RegData), .WE(WriteReg),
.Clock(Clk), .Data(WriteR
input [4:0] ReadRegSel;
input WriteReg;
output [15:0] RegData;
ram32x16 RAM_BLOCK ( .Q(RegData), .WE(WriteReg),
.Clock(Clk), .Data(WriteR
Structural HDL
EDIF,XNF, etc.

8. Synplicity Roadmap - 1998 New Products Synplify 5.0 Q2, 1998
New Products Introduced Targeting High-Density FPGA design (XC4044’s and bigger plus Virtex family)
Continued Xilinx quality of results focus Improved forward-annotation (3.0c) of timing to Alliance Series Automatic RAM inference Spreadsheet-like graphical constraints editor
Q2, 1998
April - Beta
May - Available

9. Synplify Objectives Quality of Results Designer Productivity
Optimizes across hierarchical boundaries
Conservation of design abstraction (B.E.S.T.)
Xilinx-specific technology mapping
Designer Productivity
HDL Analyst
Intuitive use model, intelligent Synplify-Xilinx defaults
Technology/Part/Package/SpeedGrade: (User Selectable)
Fanout Limit: 100
Force GSR Usage
Disable I/O Insertion (Off)
Target M1 P&R

10. The Synplify Advantage
Technology Innovations:
B.E.S.T.™ algorithms optimize across hierarchical boundaries
System level graphical timing constraint system- SCOPE™
Fast compile times for even the largest devices
Built-in timing analysis displayed through HDL Analyst
Unique Finite State Machine Compiler
Integration with popular simulators and Alliance P&R
Batch & TCL support
Easy to learn and use
Cadence endorsement of Synplify based upon technical evaluation of leading synthesis products 62

11. Timing-Driven Design SCOPE
Unifies Timing Constraints for Synthesis and P&R
Design Constraints
Clocks
define_clock CLK1 -freq 33.0
Registers
define_reg_input_delay reg_m1 5
I/Os
define_input_delay input_a 3.0
define_output_delay output_b 5.0
Multi-cycle paths
define_multicycle_path -to register_c 2
Optimization Directives (-improve)
define_reg_input_delay reg_m1 -improve 1.0
P&R Delay Compensation (-route)
define_output_delay output_a 5.0 -route 1.8
SCOPE (Synthesis Constraints OPtimization Environment)
SCOPE ™
Design Constraints:
clocks, registers, I/Os multi-cycle paths, etc.
Synplify’s Optimizer
Synplify
Timing Report
Xilinx Netlist
Alliance Place & Route
Design Constraints
and P&R
attributes
P&R Delay Compensation ( -route)
Optimization
Directive
(-improve)
Post- P&R

12. Xilinx-Specific Features
Supports all Xilinx-specific attributes
syn_maxfan, syn_noclockbuf, xc_loc, etc.
Automatic GSR usage
“black_box” support for LogiBlox / IP Cores

13. Xilinx-Specific Optimizations
Library-free synthesis maps directly to FMAPs, HMAPs and carry primitives
Module Generation
Infers counters, adders, subtractors, multipliers, etc.
Optimization & mapping across hierarchical Xilinx module boundaries
Automatically uses:
flip-flop load enable
GSR
Clock buffer resources
Carry chain resources
Automatic I/O insertion
Supports user-instantiation

14. Automatic Hierarchy Optimization
Start with design hierarchy
Perform global analysis and optimize hierarchy by creating new structure if needed
Keep existing boundaries or create new ones
Automatic time budgeting
Automatic area / time tradeoff to converge on timing goal
TOP LEVEL
A MODULE
E MODULE
H MODULE B C D F G H J K L B C D
10 ns
5 ns
15 ns
User constraint is 30ns for path from B to D

15. Unique Finite State Machine Compiler
Automatically FINDS & re-encodes FSMs
Quickly explore FSM encoding to select best implementation
67.6
92.6
60.6
94.3 36
55.6 20 40 60 80
100
Mhz
127
111 81 59 54 32 42 16 8
Number of CLBs
Number of
States
With FSM Compiler vs. Without

16. Unique Cross-Probing Provides Powerful Debugging Environment
HDL Analyst
Language Sensitive Editor Describe The Functionality
RTL View Understand/Analyze Graphically
Technology View See The Actual Technology Mapping
Unique Cross-Probing Provides
Powerful Debugging Environment

17. Critical Path Analysis in HDL Analyst
Find - Locates objects
Delay info.
Critical Paths Shows What You Need To Improve
Use Filter Schematic To Show Only the Relevant Logic

18. Summary Synplicity is Committed to Xilinx & Xilinx Users
Aggressive plan for Xilinx-specific features & new device support
Cooperative Engineering Agreement (1/98) for supporting high-density Xilinx design flows
Proprietary B.E.S.T. algorithms optimized for Xilinx devices
System level graphical constraints editor (SCOPE) separates P&R from synthesis constraints & provides full user control 72