1. Parallel Sequence Spread Spectrum (PSSS)
January 2004
Parallel Sequence Spread Spectrum (PSSS)
Andreas Wolf
Dr. Wolf & Associates
Andreas Wolf, Dr. Wolf & Associates

2. Introduction Proliferation of laptops drives WLAN demand
January 2004
Introduction
WLAN Opportunities (examples)
WLAN Challenges (examples)
Proliferation of laptops drives WLAN demand
Multimedia applications over WLAN
Wireless backbones for WLAN
Public hotspot networks
Use of WLAN in public telecommunication networks
Higher data rates, i.e. >500 Mbit/s)
More efficient spectrum use, i.e. >>2...4 Bit/s/Hz
Range, robutness, MP fading i.e. at least today’s performance
Reduced power consumption
Overcome technology barriers for further performance growth
Low cost
Andreas Wolf, Dr. Wolf & Associates

3. PSSS Characteristics January 2004 Type of system
Single carrier, spread spectrum
Signal processing and coding
Applicable over different modulations
Range & robustness
Processing gain of 15dB and higher
Coding gain > 5 dB
Highly scaleable with identical system building blocks
Specific data rate
2 bit/s/Hz bit/s/Hz, potential for > 20 bit/s/Hz
But not at the cost of robustness and/or complexity
Multipath fading
Tolerates multipath fading, similar in performance as OFDM
No add-on of TCM, Viterbi, etc.
Symbol errors
Strong robustness through underlying coding in PSSS
E.g. tolerates 21 1-value errors in 31-chip sequence without DSP or complex digital design
Implementation complexity
Shift-register digital structure in Tx
Simple ”integrate & dump” in Rx (DSSS-like reference signal)
No FFT, Viterbi etc. – low complexity
Simpler DAC / ADC (or no ADC), no approximations of analog signals
Low sensitivity against non-linearity
Low cost
Lower digital and analog complexity results in small die sizes
Overcomes barriers for performance growth in today’s technologies
Time-to-market
Use of all well-known components
Low demands in chip complexity
High reuse of existing chip designs
No need for new chip processes
Technology potential
Enables 0,5 / 1 GBit/s WLAN (in 50/100 MHz channel)
At lower chip complexity / criticality / cost than today’s 54 Mbit/s WLAN
Andreas Wolf, Dr. Wolf & Associates

4. PSSS 31 Eb/N0 versus Pb January 2004 Coding Gain  5,5 dB (pb = 1e-5)
Andreas Wolf, Dr. Wolf & Associates

5. PSSS 31 Coding Gain January 2004 PSSS 31
64 QAM
32 QAM
16 QAM
8 QAM
16PSK
8PSK
Coding Gain  5,5 dB
4PSK
PSSS 31
2PSK
pb = 1e-5
Source: John G. Proakis, Digital Communications 4th edition, McGrawHill, Boston et. al. 2001, page 282.
Andreas Wolf, Dr. Wolf & Associates

6. PSSS – Tx Architecture PSSS – PSSS 31, 88 Mbit/s (22MHz channel)
January 2004
PSSS – Tx Architecture
PSSS – PSSS 31, 88 Mbit/s (22MHz channel) PA
DAC +
Input
Data
PSSS
Encoder ~
10-15 dBc lower linearity required
PAPR 6 dB
5 bit, 44 MSPS
/2
DAC
< 1,000 gates
5 bit, 44 MSPS
OFDM – 54 MBit/s (22 MHz channel) PA
DAC +
Input
Data
Scrambler
Convolutional
Encoder
Punturer &
Bit Interleaver
Constellation
Mapping
IFFT
Insert Pilots
Add Prefix/GI ~
12/14 bit, >80 MSPS
PAPR 17 dB
/2
DAC
e.g. 40,000 gates
Digital
Analog
12/14 bit, >80 MSPS
Andreas Wolf, Dr. Wolf & Associates

7. PSSS – Rx Architecture (A)
January 2004
PSSS – Rx Architecture (A)
Pre-Select Filter
PSSS Decoder
PSSS – PSSS 31, 88 Mbit/s (22MHz channel)
LNA
Correlator
LPF 62 +
Int. & Dump
10-15 dBc
lower
linearity
required
2 transistors + RC ~
Output
Data
Output Mapping
/2
Correlator
LPF 62
Int. & Dump
2 transistors + RC
PSSS Reference
OFDM –
54 MBit/s (22 MHz channel)
< 1000 gates, 44 MSPS
124x I&D
Pre-Select Filter
Carrier Phase
and Time
Tracking
LNA
LPF
VGA
ADC
FFT
Synchronization
Remove CP +
Output
Data ~
Remove Pilots
FEQ
De-Interlaver
Viterbi
Decoder
Scrambler
De-
10/12 bit, >40 MSPS
/2
LPF
VGA
ADC
(complex)
10/12 bit, >40 MSPS
e.g. 40,000 gates,
>40 MSPS
Digital
Analog
Andreas Wolf, Dr. Wolf & Associates

8. PSSS – Rx Architecture (B)
January 2004
PSSS – Rx Architecture (B)
Pre-Select Filter
PSSS Decoder
PSSS –
PSSS 31, 88 Mbit/s (22MHz channel)
LNA
Correlator
LPF 31 +
I & D
2-bit Comp.
10-15 dBc
lower
linearity
required ~
Output
Data
Output Mapping
/2
Correlator
LPF 31
I & D
2-bit Comp.
PSSS Reference
OFDM –
54 MBit/s (20 MHz channel)
< 800 gates, 44 MSPS 62x I&D + 2-bit Comp.
Pre-Select Filter
Carrier Phase
and Time
Tracking
LNA
LPF
VGA
ADC
FFT
Synchronization
Remove CP + ~
Remove Pilots
FEQ
De-Interlaver
Viterbi
Decoder
Scrambler
De-
Output
Data
10/12 bit, >40 MSPS
/2
LPF
VGA
ADC
(complex)
10/12 bit, >40 MSPS
e.g. 40,000 gates,
>40 MSPS
Digital
Analog
Andreas Wolf, Dr. Wolf & Associates

9. Path to 1 GBit/s WLAN ? PSSS (Example) OFDM (Example) System
January 2004
Path to 1 GBit/s WLAN ?
PSSS (Example)
OFDM (Example)
System
1 Gbit/s
100 MHz channel
Single carrier or 5 carriers
1 Gbit/s,
256 QAM
Analog RF in Tx / Rx
Linearity < 25 dBc
PAPR 6 dB
Linearity > 40 dBc (?)
PAPR > 17 dB (?)
ADC / DAC
6,5 bit / 200 MSPS DAC in Tx (2x) or 5x 5 bit / 40 MSPS DAC in Tx (2x)
310 Integrate & Dump at 200 MSPS or 5x 62 Integrate & Dump at 40 MSPS
No ADC in Rx
> bit / >200 MSPS DAC in Tx
> bit / >200 MSPS ADC in Rx
(2 each)
Signal processing
None required
IFFT / FFT, > 256 points, 200 MSPS, bit
Viterbi (7/8 ?), LDPC (?)
Andreas Wolf, Dr. Wolf & Associates

10. PSSS Background Origin of the technology Status
January 2004
PSSS Background
Origin of the technology
Status
Extensive research as part of Wolf’s academic / research career
PhD in 1990: Application of SAW-based convolver for telecommunication testing
“Habilitation” in 1992: (“path” to professorship in Germany) Coding techniques for broadband ISDN [ATM] testing
Wolf has developed CCF Coding (Cross Correlation Function) as part of his habilitation in 1991
CCF is almost identical to O-QPSK used in IEEE (but used in ATM)
Wolf is named inventor in related Siemens patent (patent now owned by Tektronix)
Continued development of CCF together with Prof. Schwetlick in mid/late 1990’s
Increase of bit/s/Hz, move to wireless
”Compilation” of PSSS in 2003
Comprehensive simulations of PSSS
Reference implementation in progress
Physical proof of concept
Reference design, VHDL, bit-identical simulation bench
R&D grant from BMBF (Ministry of Research & Education, Germany)
Prototype implementation, benchmarking
Pursuing multiple partnering opportunities
Gigabit WLAN (Europe)
WLL (Asia)
Low data rate (100 Kbit/s, 4 bit/s/Hz)
Limitation ?
Coherence length of signal in PSSS effectively limits the maximum cell size
However, the resulting coherence length is still larger than typical WLAN cell sizes
Andreas Wolf, Dr. Wolf & Associates

11. Backup Simulation results PSSS31 EbN0 versus Pb January 2004
Simulation over 1 E+06 bits
Andreas Wolf, Dr. Wolf & Associates