1. EET107/3 DIGITAL ELECTRONICS 1
Chapter 3:
Sequential Logic Design
(Part 2.1)

2. 3.2 COUNTER Asynchronous counter Synchronous counter INTRODUCTION
A counter – a group of flip-flops connected together to perform counting operations.
The number of flip-flops used and the way in which they are connected determine the number of states (modulus).
Two broad categories according to the way they are clocked:
Asynchronous counter
Synchronous counter

3. SYNCHRONOUS COUNTER
A 2-bit synchronous binary counter:

4. SYNCHRONOUS COUNTER
Timing details for the 2-bit synchronous counter operation (the propagation delays of both flip-flops are assumed to be equal):

5. SYNCHRONOUS COUNTER The Binary State Sequence: CLOCK PULSE Q1 Q0
Initially 1 2 3
4 (recycles)

6. SYNCHRONOUS COUNTER
A 3-bit synchronous binary counter:

7. SYNCHRONOUS COUNTER
The Binary State Sequence for a 3-bit Binary Counter:
CLOCK PULSE Q2 Q1 Q0
Initially 1 2 3 4 5 6 7
8 (recycles)

8. SYNCHRONOUS COUNTER
A 4-bit synchronous binary counter and timing diagram. Points where the AND gate outputs are HIGH are indicated by the shaded areas.

9. SYNCHRONOUS COUNTER
A 4-Bit Synchronous BCD Decade Counter:

10. SYNCHRONOUS COUNTER The Binary State Sequence for BCD Decade Counter:
CLOCK PULSE Q3 Q2 Q1 Q0
Initially 1 2 3 4 5 6 7 8 9
10 (recycles)

11. DESIGN OF SYNCHRONOUS COUNTER
General clocked sequential circuit.

12. DESIGN OF SYNCHRONOUS COUNTER
Steps used in the design of sequential circuit:
Specify the counter sequence and draw a state diagram
Derive a next-state table from the state diagram
Develop a transition table showing the flip-flop inputs required for each transition. The transition table is always the same for a given type of flip-flop
Transfer the J and K states from the transition table to K- maps. There is a K-map for each input of each flip-flop.
Group the K-map cells to generate and derive the logic expression for each flip-flop input.
Implement the expressions with combinational logic, and combine with the flip-flops to create the counter.

13. DESIGN OF SYNCHRONOUS COUNTER
Example:
Design a Modulus-4 synchronous up-counter. Use D flip-flops.
Design a Modulus-4 synchronous up-counter. Use T flip-flops.
Design a Modulus-4 synchronous up-counter. Use JK flip-flops.
Design a Modulus-4 synchronous up-counter. Use SR flip-flops.

14. DESIGN OF SYNCHRONOUS COUNTER
Example: Design 3-bit Gray code counter by using JK, T, D and SR flip-flop.
Step 1:
State diagram for a 3-bit Gray code counter.

15. DESIGN OF SYNCHRONOUS COUNTER
Next-state table for a 3-bit Gray code counter.
Present State
Next State Q2 Q1 Q0 1

16. Transition Table for a J-K flip-flop
Output Transitions
Flip-flop Inputs QN
QN+1 J K  X 1
QN : present state
QN+1: next state
X: Don’t care

17. Karnaugh maps for present-state J and K inputs.

18. Three-bit Gray code counter.

19. Example: Design a counter with the irregular binary count sequence as shown in the state diagram. Use J-K flip-flops

20. Next-state table
Present State
Next State Q2 Q1 Q0 1

21. Transition Table for a J-K flip-flop
Output Transitions
Flip-flop Inputs QN
QN+1 J K  X 1

22. K-MAP

23. The Counter Circuit

24. Example : State diagram for a 3-bit up/down Gray code counter.

25. The 74HC163 4-bit synchronous binary counter
The 74HC163 4-bit synchronous binary counter. (The qualifying label CTR DIV 16 indicates a counter with sixteen states.)

26. Timing example for a 74HC163.

27. The 74LS160 synchronous BCD decade counter
The 74LS160 synchronous BCD decade counter. (The qualifying label CTR DIV 10 indicates a counter with ten states.)

28. Timing example for a 74LS160.

29. UP/DOWN SYNCHRONOUS COUNTER A basic 3-bit up/down synchronous counter.

30. Timing Diagram

31. The 74HC190 up/down synchronous decade counter.

32. Timing example for a 74HC190.

33. J and K maps for Table 9-11. The UP/DOWN control input, Y, is treated as a fourth variable.

34. Three-bit up/down Gray code counter.

35. CASCADE COUNTERS
Two cascaded counters (all J and K inputs are HIGH).

36. A modulus-100 counter using two cascaded decade counters.

37. Three cascaded decade counters forming a divide-by-1000 frequency divider with intermediate divide- by-10 and divide-by-100 outputs.

38. Example: Determine the overall modulus of the two cascaded counter for (a) and (b)
For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536 for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400

39. A divide-by-100 counter using two 74LS160 decade counters.

40. A divide-by-40,000 counter using 74HC161 4-bit binary counters
A divide-by-40,000 counter using 74HC161 4-bit binary counters. Note that each of the parallel data inputs is shown in binary order (the right-most bit D0 is the LSB in each counter).

41. COUNTER DECODING
* To determine when the counter is in a certain states in its sequence by using decoders or logic gates.
Decoding of state 6 (110).

42. A 3-bit counter with active-HIGH decoding of count 2 and count 7.

43. A basic decade (BCD) counter and decoder.

44. Outputs with glitches from the previous decoder
Outputs with glitches from the previous decoder. Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

45. The basic decade counter and decoder with strobing to eliminate glitches.

46. Strobed decoder outputs for the circuit

47. Simplified logic diagram for a 12-hour digital clock.

48. Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

49. Logic diagram for hours counter and decoders
Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

50. Functional block diagram for parking garage control.

51. Logic diagram for modulus-100 up/down counter for automobile parking control.

52. Parallel-to-serial data conversion logic.

53. Example of parallel-to-serial conversion timing for the previous circuit

54. THANK YOU