Presentation is loading. Please wait.

Presentation is loading. Please wait.

L21 – Register Set.

Published byΆφροδίτη Κομνηνός Modified over 5 years ago

Similar presentations

Presentation on theme: "L21 – Register Set."— Presentation transcript:

1 L21 – Register Set

2 Dual Ported Register Set
Testing of a dual ported register set Ref: text Unit 10, 17, 20 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

3 Copyright 2012 - Joanne DeGroat, ECE, OSU
The objective Dual ported register set 2 data busses Can load or drive either bus No timing – only control To insure this unit will synthesize need to do it subcomponent by subcomponent and structurally. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

4 Copyright 2012 - Joanne DeGroat, ECE, OSU
From last time The next step is the VHDL simulation of the register set to be sure its behavior is as desired. First step is to establish the interface and control signal setup and bus timing. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

5 Copyright 2012 - Joanne DeGroat, ECE, OSU
Bus timing Note the polarity of control signals and that source keep data on bus long enough. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

6 Copyright 2012 - Joanne DeGroat, ECE, OSU
Now look to design Decoders for register number are straight combination logic. Testing (demo) shows that output of drivers could be the problem. Equation is adr1 <= asel(0) and adrive Asel(i) is a 1 when it is the selected register From timing adrive is active low. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

7 Copyright 2012 - Joanne DeGroat, ECE, OSU
The architecture Initial debugging pointed to the output driver logic 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

8 The testbench setup – the start
-- Test Bench Entity for the Register set -- NEEDS modification for 3561 register set ENTITY rtst IS END rtst; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ARCHITECTURE test OF rtst IS COMPONENT reg_set_4 IS PORT ( ABUS,BBUS : INOUT std_logic_vector; Aload,Bload : IN std_logic; Adrive,Bdrive : IN std_logic; AregNo,BregNo : IN std_logic_vector(1 downto 0)); END COMPONENT; FOR ALL : reg_set_4 USE ENTITY WORK.reg_set_4(one); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

9 Copyright 2012 - Joanne DeGroat, ECE, OSU
Local Declarations SIGNAL ABUS,BBUS : std_logic_vector (7 downto 0); SIGNAL Aload,Bload,Adrive,Bdrive : std_logic; SIGNAL Aloadc,Bloadc,Adrivec,Bdrivec : std_logic; SIGNAL AregNo,BregNo : std_logic_vector(1 downto 0); CONSTANT HighZ : std_logic_vector (7 downto 0) := "ZZZZZZZZ"; TYPE vals_type IS array (0 to 3) of std_logic_vector (7 downto 0); CONSTANT Vals : vals_type := (" "," ", " "," "); SIGNAL Abus_err, Bbus_err : BIT; TYPE regno_type IS array (0 to 3) of std_logic_vector (1 downto 0); CONSTANT regno : regno_type := ("00","01","10","11"); TYPE LDItype IS (Load,Drive,Idle); BEGIN 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

10 Component instantiation
r0 : reg_set_4 PORT MAP (ABUS,BBUS,Aloadc,Bloadc,Adrivec,Bdrivec,AregNo,BregNo); --check for signal polarity – error debugging Aloadc <= Aload; Bloadc <= Bload; Adrivec <= Adrive; Bdrivec <= Bdrive; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

11 Copyright 2012 - Joanne DeGroat, ECE, OSU
Run the bus cycle applytest : PROCESS PROCEDURE applyNtest (A_ldi : LDItype; A_reg_no : std_logic_vector(1 downto 0); A_BUS_VAL : std_logic_vector (7 downto 0); A_BUS_EXP : std_logic_vector (7 downto 0); B_ldi : LDItype; B_reg_no : std_logic_vector(1 downto 0); B_BUS_VAL : std_logic_vector (7 downto 0); B_BUS_EXP : std_logic_vector (7 downto 0)) IS BEGIN WAIT FOR 9 NS; ns into cycle IF (ABUS /= HighZ) THEN Abus_err <= '1','0' after 1 ns; END IF; IF (BBUS /= HighZ) THEN Bbus_err <= '1','0' after 1 ns; END IF; WAIT FOR 1 NS; ns into cycle BUS PROTOCOL is such that 1st 10 ns of bus cycle should have the bus at high Z. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

12 Copyright 2012 - Joanne DeGroat, ECE, OSU
Now setup control sigs. AregNo <= A_reg_no; BregNo <= B_reg_no; CASE A_ldi IS WHEN Load => Aload <= '0'; ABUS <= A_BUS_VAL; WHEN Drive => Adrive <= '0'; WHEN Idle => null; END CASE; CASE B_ldi IS WHEN Load => Bload <= '0'; BBUS <= B_BUS_VAL; WHEN Drive => Bdrive <= '0'; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

13 Was value driven onto the bus
WAIT FOR 10 NS; ns into cycle IF (ABUS /= A_BUS_EXP) THEN Abus_err <= '1','0' after 1 ns; END IF; IF (BBUS /= B_BUS_EXP) THEN Bbus_err <= '1','0' after 1 ns; END IF; WAIT FOR 49 NS; ns into cycle 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

14 The load, drive signals return high
WAIT FOR 1 NS; ns into cycle IF (A_ldi = Load) THEN Aload <= '1'; END IF; IF (B_ldi = Load) THEN Bload <= '1'; END IF; WAIT FOR 10 NS; ns into cycle IF (A_ldi = Drive) THEN Adrive <= '1'; ELSE ABUS <= HighZ; END IF; IF (B_ldi = Drive) THEN Bdrive <= '1'; ELSE BBUS <= HighZ; END IF; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

15 A final check at end of cycle
Be sure a return to high Z\ WAIT FOR 11 NS; ns into cycle IF (ABUS /= HighZ) THEN Abus_err <= '1','0' after 1 ns; END IF; IF (BBUS /= HighZ) THEN Bbus_err <= '1','0' after 1 ns; END IF; WAIT FOR 9 NS; -- end of 100 ns cycle END applyNtest; 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

16 Copyright 2012 - Joanne DeGroat, ECE, OSU
BEGIN of the Process BEGIN -- set initial values ABUS <= HighZ; BBUS <= HighZ; AregNo <= regno(0); BregNo <= regno(0); Aload <= '1'; Bload <= '1'; Adrive <= '1'; Bdrive <= '1'; -- TEST LOADING AND READING VALUES ONE AT A TIME 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

17 Copyright 2012 - Joanne DeGroat, ECE, OSU
Load from A bus FOR I in 0 to 3 Loop -- load values into register I using A bus and redrive it on A bus FOR J in 0 to 3 LOOP applyNtest(load,regno(I),Vals(J),Vals(J),idle,regno(I),HighZ,HighZ); applyNtest(drive,regno(I),HighZ,Vals(J),idle,regno(I),HighZ,HighZ); END LOOP; -- drive last value input into register I onto B bus applyNtest(idle,regno(I),HighZ,HighZ,drive,regno(I),HighZ,Vals(3)); 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

18 Copyright 2012 - Joanne DeGroat, ECE, OSU
Load from B bus -- load values into register I using B bus and redrive it on B bus FOR J in 0 to 3 LOOP applyNtest(idle,regno(I),HighZ,HighZ,load,regno(I),Vals(J),Vals(J)); applyNtest(idle,regno(I),HighZ,HighZ,drive,regno(I),HighZ,Vals(J)); END LOOP; -- drive last value onto A Bus applyNtest(drive,regno(I),HighZ,Vals(3),idle,regno(I),HighZ,HighZ); END Loop; Here there are problems – the value does not seem to be latched into the register. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

19 Copyright 2012 - Joanne DeGroat, ECE, OSU
Simulation results Waveform for the first 2 load n drive cycles 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

20 Copyright 2012 - Joanne DeGroat, ECE, OSU
Simulation results The next 500 ns of simulation 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

21 Copyright 2012 - Joanne DeGroat, ECE, OSU
Lecture summary Have seen how to create a 4 register location register-set. The next assignment is to use the code here (which is also on the web page) to generate a 8 location register. Simply build upon this code. 9/2/2012 – ECE 3561 Lect 9 Copyright Joanne DeGroat, ECE, OSU

Download ppt "L21 – Register Set."

Similar presentations

1/8/2007 - 27 VerilogCopyright 2006 - Joanne DeGroat, ECE, OSU1 Verilog Overview An overview of the Verilog HDL.

1/8/ VerilogCopyright Joanne DeGroat, ECE, OSU1 Verilog Overview An overview of the Verilog HDL.
L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.

L23 – Adder Architectures. Adders  Carry Lookahead adder  Carry select adder (staged)  Carry Multiplexed Adder  Ref: text Unit 15 9/2/2012 – ECE 3561.
EE694v-Verification-Lect6-1- Lecture 6 - Writing Tests A difference if treating the design as a black box or if you have access to internal signals EE762.

EE694v-Verification-Lect6-1- Lecture 6 - Writing Tests A difference if treating the design as a black box or if you have access to internal signals EE762.
1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.
L18 – VHDL for other counters and controllers. Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit.

L18 – VHDL for other counters and controllers. Other counters  More examples Gray Code counter Controlled counters  Up down counter  Ref: text Unit.
Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.

Quad 2-to-1 and Quad 4-to-1 Multiplexers Discussion D2.4 Example 7.
Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.

Kazi Fall 2006 EEGN 4941 EEGN-494 HDL Design Principles for VLSI/FPGAs Khurram Kazi Some of the slides were taken from K Gaj’s lecture slides from GMU’s.
Simple Testbenches Behavioral Modeling of Combinational Logic

Simple Testbenches Behavioral Modeling of Combinational Logic
L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.

L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.
ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.

ECE 332 Digital Electronics and Logic Design Lab Lab 5 VHDL Design Styles Testbenches.
L16 – Testbenches for state machines. VHDL Language Elements  More examples HDL coding of class examples Testbench for example  Testing of examples.

L16 – Testbenches for state machines. VHDL Language Elements  More examples HDL coding of class examples Testbench for example  Testing of examples.
L26 – Datapath ALU implementation

L26 – Datapath ALU implementation
L16 – VHDL for State Machines with binary encoding.

L16 – VHDL for State Machines with binary encoding.
1/8/2007 - L7 Project Step 3Copyright 2006 - Joanne DeGroat, ECE, OSU1 Project Step 3 Structural Modeling and the Generate Statement.

1/8/ L7 Project Step 3Copyright Joanne DeGroat, ECE, OSU1 Project Step 3 Structural Modeling and the Generate Statement.
L12 – VHDL Overview. VHDL Overview  HDL history and background  HDL CAD systems  HDL view of design  Low level HDL examples  Ref: text Unit 10, 17,

L12 – VHDL Overview. VHDL Overview  HDL history and background  HDL CAD systems  HDL view of design  Low level HDL examples  Ref: text Unit 10, 17,
Mixed Style RTL Modeling

Mixed Style RTL Modeling
L19 – Resolved Signals. Resolved Signals  What are resolved signals In systems In VHDL Resolution – Isn’t that for resolving conflicts?  Ref: text Unit.

L19 – Resolved Signals. Resolved Signals  What are resolved signals In systems In VHDL Resolution – Isn’t that for resolving conflicts?  Ref: text Unit.
4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.

4-to-1 Multiplexer: Module Instantiation Discussion D2.2 Example 5.
2/10/07DSD,USIT,GGSIPU1 BCD adder KB3B2B1B0CD3D2D1D0 0000000000 0000100001 0001000010 0001100011 0010000100 0010100101 0011000110 0011100111 0100001000.

2/10/07DSD,USIT,GGSIPU1 BCD adder KB3B2B1B0CD3D2D1D
L20 – Register Set. The 430 Register Set  Not exactly a dual ported register set, but a dual drive register set.  Ref: text Unit 10, 17, 20 9/2/2012.

L20 – Register Set. The 430 Register Set  Not exactly a dual ported register set, but a dual drive register set.  Ref: text Unit 10, 17, 20 9/2/2012.

Similar presentations

Ads by Google