1. Chapter 6
Memory
Linda Null, Julia Lobur

2. Figure 06. UN01: "RAM/abr. /: Rarely Adequate Memory
Figure 06.UN01: "RAM/abr./: Rarely Adequate Memory. because the more memory a computer has, the faster it can produce error messages." - Anonymous
Anonymous

3. Figure 06. UN02: "640k [of memory] ought to be enough for anybody
Figure 06.UN02: "640k [of memory] ought to be enough for anybody." - Anonymous
CREDIT UPDATE NEEDED: Anonymous

4. Figure 06.F01: The Memory Hierarchy-

5. Figure 06.F02: Direct Mapping of Main Memory Blocks to Cache Blocks-

6. Figure 06.F03: The Format of a Main Memory Address Using Direct Mapping-

7. Figure 06.F04: Diagrams for Example 6.1-

8. Figure 06.F05: The Main Memory Address Format for Example 6.2-

9. Figure 06.F06: The Memory from Example 6.3 Mapped to Cache-

10. Figure 06.F07: The Main Memory Address Format for Example 6.3-

11. Figure 06.F08: The Main Memory Address 9 = 1001₂ Split into Fields-

12. Figure 06.F09: Associative Cache-

13. Figure 06.F10: The Main Memory Address Format for Associative Mapping-

14. Figure 06.F11: A 2-Way Set Associative Cache

15. Figure 06.F12: Format for Set Associative Mapping for Example 6.5-

16. Figure 06.F13: Direct Mapped Memory Format for Example 6.6-

17. Figure 06. F14: The Address 0x326A0 from Example 6
Figure 06.F14: The Address 0x326A0 from Example 6.6 Divided into Fields for Direct Mapping -

18. Figure 06.F15: Fully Associative Memory Format for Example 6.6-

19. Figure 06.F16: 4-Set Associative Mapped Memory Format for Example 6.6

20. Figure 06. F17: The Address 0x326A0 from Example 6
Figure 06.F17: The Address 0x326A0 from Example 6.6 Divided into Fields for Set Associative Mapping -

21. Figure 06.F18: Current State Using Paging and Associated Page Table-

22. Figure 06.F19: Format for an 8-Bit Virtual Address with 25 = 32 Byte Page Size

23. Figure 06.F20: Format for Virtual Address 000011012 = 0x0D-

24. Figure 06.F21: Format for Physical Address 10011012 = 4D16-

25. Figure 06.F22: A Small Memory from Example 6.8 Using Paging-

26. Figure 06.F23: A Larger Memory Example Using Paging-

27. Figure 06.F24: Format for Virtual Address 0x1211232A-

28. Figure 06.F25: Format for physical address 0x3F00F32A-

29. Figure 06.F26: Current State of the TLB for Figure 6.23-

30. Figure 06.F27: Using the TLB -

31. Figure 06.F28: Putting It All Together: The TLB, Page Table, Cache, and Main Memory-

32. Figure 06.F29: Pentium Memory Hierarchy-