1. Floating Point Hardware and Algorithms
Ch.3
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2. Review Adder gate level diagram Adder Verilog module
Processing Verilog files using Icarus Verilog
Simulation verilog module definition using vvp
Floating point representation
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3. Adder Circuit
Adder (a,b,cin)  s, cout
s = ?
cout = ?
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4. Processing Verilog File
Icarus Verilog, vvp are the tools available on cse machines
Icarus Verilog compiler: iverilog
iverilog is a compiler that translates Verilog source code into executable programs for simulation, or other netlist formats for further processing. The currently supported targets are vvp for simulation
vvp is the run time engine that executes the default compiled form generated by Icarus Verilog. The output from the iverilog command is not by itself executable on any plat form. Instead, the vvp program is invoked to execute the generated output file.
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5. Using the Verilog Compiler and Runtime
Design your Verilog module according to the specification given
For adder, lets say we have saved the verilog module design in “adder.v”
Compile the module definition into a form that can be executed by vvp runtime.
iverilog -o adder adder.v
Output of iverilog command is stored in file “adder”
Run the code to check the output, that is typically generated by the tester code.
vvp adder
You will see the output on the screen
You can also capture into a file to submit it or print it.
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6. Floating point numbers
Why do we need them?
To represent very large number and very small number.
To represent a larger range of number with a given size in bits.
Consider a 4 bit container
Consider a 8 bit container
Examples: An astronautical unit (Au)is the distance between the earth and the sun in meters.
150,000,000,000 meters
Size of Helium atom: 1 angstrom: meters
See more details on units of measurement here
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7. FP Representation S Exponent Fraction Value = (-1)S X F X 2 E
32 bit single precision
64 bit double precision
IEEE 754 format
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8. FP Addition and Multiplication
Components: operands, ALU, control, comparison, shifters, normalize, round
Control
ALUs
Figures: 3.17, 3.16, 3.18
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