1. Excitation Vectors
Input
Combinational Logic
Memory
Output
States

2. RS Latch
Q+ = S + R’ Q
Two Problems:
R=S= 1 Not allowed, Data is transparent

3. The D Latch
Problem: Level sensitive

4. JK Latch : Universal, Level sensitive,
Timing Constraints due to feed back.

5. Master Slave Flip Flop
Edge sensitive,Set up and Hold time

6. Master Slave Flip Flop Edge sensitive,-Falling Edge
Set Up and Hold Time constraints
Path to setup data
Master
Slave D D Q Q Q D D D
Latch
Latch Q C C C
Path to hold data D C Q

7. Edge triggered Flip Flop:
Set up and Hold time Constraints

8. Edge Triggered, D Flip Flop
NAND1 S Q
NAND2
NAND5
clk R
NAND3
NAND6 D
NAND4
reset

9. When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3
Case2, D=1 tsetup=t4 + t1 thold= t2
clk D
reset Q
NAND1
NAND2
NAND3
NAND4
NAND5
NAND6 S R

10. When CLK changes from 0 to 1 Case1, D=0: tsetup= t4, thold=t3
reset Q
NAND1
NAND2
NAND3
NAND4
NAND5
NAND6 S R
Path for hold
Path for set up

11. When CLK changes from 0 to 1 Case2, D=1 tsetup=t4 + t1 thold= t2
Path to set up
clk D
reset Q
NAND1
NAND2
NAND3
NAND4
NAND5
NAND6 S R
Path to hold

12. D Flip Flop