1. Review Lectures
Mar. 31 – April
Note:

2. Assignments
Ass1: 2.1, 2.2, 2.5, 2.6, 2.7, 2.9
Ass2: 3.1, 3.3, 3.4, 3.5, 3.6, 3.7
Ass3: 3.9 (switch logic), 3.13, 3.15, 3.16, 3.17, , 5.1, 5.4
VHDL and Verilog: one-bit full-adder
Note:

3. Review Chapter 1: Overview Chapter 2 : 2.1, 2.2 Fabrication steps
2.3.1 – Simple transistor model and tub tie and latch up
current, voltage and gate capacitance
wires and vias
Design rules and stick diagram
Note:

4. Midterm Review (cont’d)
 3. Chapter 3
3.1, Combination logic
3.3 – Noise margin, delay, power consumption
driving large load, switch logic,
Peseudo-nMOS, Domino, RC transmission line
Chapter 5: latch and flip-flop
5. Notes: Scale, yield, routing, simulation, VHDL/Verilog, adder, memory, FPGA
Note:

5. Examples
Note:

6. Final
TBA
Note: