1. Basic Adders and Counters Implementation of Adders
ECE 645: Lecture 1
Basic Adders and Counters
Implementation of Adders
in FPGAs

2. Required Reading Behrooz Parhami,
Computer Arithmetic: Algorithms and Hardware Design
Chapter 5, Basic Addition and Counting,
Sections , pp

3. Required Reading Spartan-3 Generation FPGA User Guide
Chapter 9, Using Carry and Arithmetic Logic

4. Half-adder c x HA s y x y c s 1 1 1 1
2 1
x + y = ( c s )2

5. Alternative implementations (1)
Half-adder
Alternative implementations (1) a)
c = xy
s = x  y b)
s = xy + xy
c = x + y

6. Alternative implementations (2)
Half-adder
Alternative implementations (2) c)
c = xy
s = xc + yc = xc  yc

7. Full-adder x cout FA y s cin x + y + cin = ( cout s )2 x y cin cout s1 1 1 1 1
x + y + cin = ( cout s )2

8. Alternative implementations (2)
Full-adder
Alternative implementations (2) a)
s = x  y  cin = xycin + xycin + xycin + xycin
cout = xy + xcin + ycin

9. Alternative implementations (1)
Full-adder
Alternative implementations (1) b)
s = (x  y)  cin
cout = xy + cin (x  y) s c

10. Alternative implementations (3)
Full-adder
Alternative implementations (3) c) x y
cout s 1
cin

11. Alternative implementations (4)
Full-adder
Alternative implementations (4)
Implementation used to generate fast carry logic
in Xilinx FPGAs x y A2 A1
XOR D 1
Cin
Cout S p g x y
cout 1
cin
p = x  y
g = y
s= p  cin = x  y  cin

15. Latency of a k-bit ripple-carry adder
dRCA(k) = dFA(x,ycout) +
+ (k-2)  dFA(cincout) +
dFA(cin s)
Latency = ak + b

17. Unsigned addition vs. signed addition
Programmer
Machine
Unsigned
mind
Signed
mind
weight
carry 1 1 1 X Y S + = x7 y7 x6 y6 x5 y5 x4 y4 x3 y3 x2 y2 x1 y1 x0 y0 FA FA FA FA FA FA FA FA c8 c7 c6 c5 c4 c3 c2 c1 s7 s6 s5 s4 s3 s2 s1 s0

18. Out of range flags Carry flag - C C = 1 if result > MAX_UNSIGNED or
out-of-range for unsigned numbers
C = if result > MAX_UNSIGNED or
result < 0
otherwise
where MAX_UNSIGNED = for 8-bit operands
216-1 for 16-bit operands
Overflow flag - V
out-of-range for signed numbers
V = if result > MAX_SIGNED or
result < MIN_SIGNED
otherwise
where MAX_SIGNED = for 8-bit operands
for 16-bit operands
MIN_SIGNED = for 8-bit operands
for 16-bit operands

19. Overflow for signed numbers
Indication of overflow
Positive
+ Positive
= Negative
Negative
+ Negative
= Positive
Formulas
Overflow2’s complement = xk-1 yk-1 sk-1 + xk-1 yk-1 sk-1

20. Addition of Signed and Unsigned Numbers
C=1 and V=0 ≠8
C=0 and V=1
≠-7

21. Addition of Signed and Unsigned Numbers
C=0 and V=0
C=1 and V=1 ≠7
≠-7

22. Two’s complement representation of signed integers+0 +1 +2 +3 +4 +5 +6 +7 +8 +9
+10
+11
+12
+13
+14
+15

24. Overflow for signed numbers (1)
Indication of overflow
Positive
+ Positive
= Negative
Negative
+ Negative
= Positive
Formulas
Overflow2’s complement = xk-1 yk-1 sk-1 + xk-1 yk-1 sk-1 =
= ck  ck-1

25. Overflow for signed numbers (2)
xk-1 yk-1 ck-1 ck sk-1 overflow ckck-1 1 1 1 1 1 1 1

26. Implementation of Adders in FPGAs

27. Xilinx FPGA Devices Technology Low-cost High-performance 220 nm
Spartan II
Virtex
120/150 nm
Virtex II, II Pro
90 nm
Spartan 3
Virtex 4
65 nm
Virtex 5
45 nm
Spartan 6
40 nm
Virtex 6
28 nm
Artix 7
Virtex 7

28. Altera FPGA Devices Technology Low-cost Mid-range High-performance
130 nm
Cyclone
Stratix
90 nm
Cyclone II
Stratix II
65 nm
Cyclone III
Arria I
Stratix III
40 nm
Cyclone IV
Arria II
Stratix IV
28 nm
Cyclone V
Arria V
Stratix V

29. General structure of an FPGA
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

31. Xilinx Spartan 3 FPGAs
The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (

32. CLB Slice Structure Each slice contains two sets of the following:
Four-input LUT
Any 4-input logic function,
or 16-bit x 1 sync RAM (SLICEM only)
or 16-bit shift register (SLICEM only)
Carry & Control
Fast arithmetic logic
Multiplier logic
Multiplexer logic
Storage element
Latch or flip-flop
Set and reset
True or inverted inputs
Sync. or async. control
Two slices form a CLB. These slices can be used independently or together for wider logic functions.Within each slice also, the LUT and the flip flop can be used for the same function or for independent functions. The flip flops do not handcuff the designers into only having a set or clear. And for more ASIC like flows, the flip flop can be sued as latch. So, the designers do not need to re-code the design for the device architecture.

33. Carry & Control Logic SLICE Carry & Control Logic Carry & Control
COUT YB
Look-Up
Table
Carry
&
Control
Logic Y G4 G3 G2 G1 S D Q O CK EC R
F5IN BY SR XB
Look-Up
Table
Carry
&
Control
Logic X S F4 F3 F2 F1 D Q O
The configurable logic block (CLB) contains two slices. Each slice contains two 4-input look-up tables (LUT), carry & control logic and two registers. There are two 3-state buffers associated with each CLB, that can be accessed by all the outputs of a CLB.
Xilinx is the only major FPGA vendor that provides dedicated resources for on-chip 3-state bussing. This feature can increase the performance and lower the CLB utilization for wide multiplex functions. The Xilinx internal bus can also be extended off chip. CK EC R
CIN
CLK CE
SLICE

34. Carry & Control Logic in Xilinx FPGAs
COUT 1 1 x y y
CIN
CIN
Propagate = x  y
Generate = y
Sum= Propagate  CIN = x  y  CIN

35. Carry & Control Logic in Spartan 3 FPGAsx y
LUT
Hardwired (fast) logic

36. Simplified View of Spartan-3 FPGA Carry and Arithmetic Logic in One
Logic Cell x y

37. Simplified View of Carry Logic in One Spartan 3 Slice

39. Critical Path for an
Adder Implemented Using
Xilinx Spartan 3 FPGAs

40. Number and Length of Carry Chains
for Spartan 3 FPGAs

41. Bottom Operand Input to Carry Out Delay
TOPCYF
0.9 ns for Spartan 3

42. Carry Propagation Delay
tBYP
0.2 ns for Spartan 3

43. Carry Input to Top Sum Combinational Output Delay
TCINY
1.2 ns for Spartan 3

44. Critical Path Delays and Maximum Clock Frequencies
(taking into account surrounding registers)

45. Major Differences between Xilinx Families
Spartan 3
Virtex 4
Virtex 5, Virtex 6,
Spartan 6
Look-Up Tables
4-input
6-input
Number of CLB slices
per CLB 4 2
Number of LUTs
per CLB slice 2 4
Number of adder
stages per CLB slice 2 4

46. Logic Element (LE) – Normal Mode
Altera Cyclone III
Logic Element (LE) – Normal Mode

47. Logic Element (LE) – Arithmetic Mode
Altera Cyclone III
Logic Element (LE) – Arithmetic Mode

48. Altera Stratix III, Stratix IV
Adaptive Logic Modules (ALM) – Normal Mode

49. Altera Stratix III, Stratix IV
Adaptive Logic Modules (ALM) – Arithmetic Mode

50. Addition of a Constant

51. Addition of a constant (1)
xk-1 xk x1 x0
yk-1 yk y1 y0
variable +
constant
sk-1 sk s1 s0
xk-1 xk xh+1 xh xh x0
yk-1 yk yh
variable +
constant
sk-1 sk sh+1
xh xh x0

52. Addition of a constant (2)
. . .
xk-1
xk-2
xh+2
xh+1 xh
xh-1 x0
. . . ck
. .
. . .
HA/
MHA
HA/
MHA
HA/
MHA
HA/
MHA
sk-1
sk-2
. . .
sh+2
sh+1 xh
xh-1
. . . x0 If
yi = Half-adder (HA)
yi = Modified half-adder (MHA)

53. Modified half-adder c x MHA s y x y c s 1 1 1 1 x + y + 1 = ( c s )21 1 1 1
2 1
x + y + 1 = ( c s )2

54. Incrementer xk-1 xk-2 x2 x1 x0 . . . ck . . sk-1 sk-2 . . . s2 s1 x0HA HA HA HA
sk-1
sk-2
. . . s2 s1 x0
Decrementer
xk-1
xk-2 x2 x1 x0
. . . ck
. .
MHA
MHA
MHA
MHA
sk-1
sk-2
. . . s2 s1 x0

57. Bit-Serial & Digit-Serial Adders

59. xi yi
Bit-serial
adder c0
ci+1
start
clk si

60. xi yi d d
Digit-serial adder c0
ci+1
start
clk d si

61. Asynchronous Adders

62. Possible solutions to the carry propagate problem
1. Detect the end of propagation rather than wait for
the worst-case time
2. Speed-up propagation via
look-ahead
carry skip
carry select, etc
3. Limit carry propagation to within a small number of bits
4. Eliminate carry propagation through the redundant
number representation

64. Analysis of carry propagation
Probability of carry generation = (xiyi = 11)
Probability of carry propagation = (xiyi = 01 or 10)
Probability of carry anihilation = (xiyi = 00 or 11)
j j i+1 i
1 0 … 1 …0 … 1 1
1 1 … 0 …1 … 0 1
11 or 00
01 or 10
Probability of
carry propagating
from position
i to position j =  =
probability of
propagation
probability of
anihilation

65. Expected length of the carry chain that starts at position i (1)
Expected length(i, k) =
Length
of the
carry chain
Probability
of the given
length
Distance
till the end
of adder
Probability
of propagation
till the end of
adder

66. Expected length of the carry chain that starts at position i (2)
Expected length(i, k) =
For i << k
Expected length of the carry propagation is  2