1. Packet Classification with Evolvable Hardware Hash Functions
Harald Widiger, Mathias Handy, Dirk Timmermann
University of Rostock
Institute of Applied Microelectronics
and Computer Science

2. Packet Classification and Hash Functions
Packet Classification Problem: In huge rule sets a search takes much time and/or demands huge memories
Hash functions have a search complexity of ideally O(1) and memory demand of O(N)
Problem when using (hardware) hash functions:
High performance for different key sets
Low hardware costs for a hardware implementation
Bandwidth demands of communication networks are rising permanently. Thus, the requirements to modern routers regarding packet classification are rising accordingly.
Packet Classification means finding rules which corresponds to a key extracted from a packet.
Conventional algorithms must make a trade­off between classification speed and memory demands.
By the use of a hash function both demands can be met. Hash functions have a search complexity of ideally O(1). Thus, they are independent of the number of elements searched in. With O(N) the memory need scales only linearly with the number of elements.
However, it is problematic to find a sufficient hash function. It has to be both high performance and of low hard­ware costs.

3. Evolvable Hardware
Goal: High performance for different and changing key set with low hardware costs
Solution: a function which can adapt constantly and autonomously to an actual key set  evolvable hardware
As stated before a hash function for packet classification must meet two demands
It must have a high performance for different key sets
It must not have very high implementation costs
A solution for this problem is a permanently adapting and improving hash function. This goal can be obtained by evolutionary computing completely done in hardware. Such an evolvable hardware hash function is proposed is this presentation.

4. Hardware Hash Function
Architecture of an evolvable hash function can be seen:
The function hashes an N-bit wide key to an M-Bit wide hash value
It consists N to 1 Multiplexers, which are controlled by an log2(N)-bit wide register
for every bit of the hash value two of those multiplexers are connected together by an xor-function
therefore the functionality of the hash function is determined by 2*M*log2(N) registers
The registers form the genome of the evolvable hardware hash function (By the change of one bit other input bits are multiplexed to the output of the hash function
Genomesize:

5. System Architecture
Hardware consists of a datapath and an evolution module
In the datapath the packet classification is done by finding classification rules for incoming frames with the help of the hash functions
The evolution module changes the hash function depending on the existing key to increase lookup performance
Hardware consist of two main components The Data Path and the Evolution module
In The Data Path every incoming packet is classified by finding a corresponding rule:
A key is extracted from the frame
The key is hashed
the hash value is taken as address in the rule memory
memory is searched until the correct classification rule is found
the data path then outputs the rule together with the frame
To increase the lookup performance the hash function used for the packet classification is evolved depending on the used key set
This way the lookup performance betters constantly and incoming frames can be classified with high speed

6. Evolutionary Algorithm
Evolution Module will consist of six functional elements as can be seen in the block diagram:
The evolutionary algorithm performed by the hardware has the following features
Four individuals holding the genome of a hash function
The individuals produce an offspring of twelve randomly
The offspring is mutated with a bit mutation probability of 1/N (genome consists of N bit)
For all twelve offspring elements the implemented hash function is reconfigured and the fitness is evaluated
From the twelve offspring and the fittest parent the four fittest individuals are selected to form the next generation
Fitness evaluation:
All existing keys are hashed into a memory the number of collisions is counted. This value is taken as fitness value
That means: The lesser the value the better. A perfect hash function produces no collisions.

7. Simulation Results
Simulation Results of the evolvable hardware hash functions:
different hash functions implemented as a SystemC model (hash2 is the one mentioned before)
functional identical to the hardware implementation
function was evaluated with different keys up to 217 randomly generated keys
graph reveals, that the different architectures performed differently:
best performance shows hash2:
with a memory load of 50% less than 4 memory accesses are needed in the average
with a memory load of 75% number of accesses remains below 6
outperform the needed 16 memory accesses of a sorted list remarkably
However, theoretical upper bound for finding an entry is still O(N). The required memory accesses for some key is far more than log2(N)

8. Outlook Hardware implementation into an FPGA
Simulation of the lookup performance with real rules sets
Improvement of the performance of the fitness evaluation
Finally implementation in a dynamically reconfigurable environment
There are numerous task left, which must be executed.
First off all, the system has to be fully implemented into an FPGA and tested on a evaluation board.
The simulations must be done with real rule sets from routers instead of randomly generated key sets to evaluate the performance when keys are correlated
The fitness evaluation as mentioned here is very time consuming. The speed of the evaluation must be increased
parallel evaluation for all elements of the offspring
memory interleaving for collision resolution
Finally, the packet classifier is to be implemented into a dynamically reconfigurable environment. That means no multiplexers are needed for the hardware implementation of the hash functions just xor-connected wires