1. L25 – Datapath ALU

2. Copyright 2012 - Joanne DeGroat, ECE, OSU
Datapath ALU
The full ALU
Incorporating ALU into datapath
From Datapath to microprocessor
Ref: text and basic computer architecture books
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

3. Copyright 2012 - Joanne DeGroat, ECE, OSU
The full ALU
ALU does both arithmetic and logic operations.
For the logic operations use a 4-to-1 multiplexer and ALU can do any logic operation on two bits.
Arithmetic operations are add (no carry), add with carry, subtract (2’s complement), subtract with borrow, increment, and decrement.
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

4. Copyright 2012 - Joanne DeGroat, ECE, OSU
The structure
The internal ALU structure
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

5. Incorporating into datapath
Take ALU component, add input registers and output bus driver
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

6. How to approach this in quartis
Have the register set.
Build up the ALU unit
But how to build up the ALU unit?
Assignment HW 12 – Create the core of the ALU unit – an add unit, a logic unit (4-to-1 mux), the 2-to-1 Mux for selecting the output from which unit, and the internal controller. Note that there will be several interface signals to the units.
MUX – the function control signals (4), A, B
Adder – A,B, the carry in
OUTPUT Mux – L, R, select
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

7. Copyright 2012 - Joanne DeGroat, ECE, OSU
Assignment HW12
Create the blocks
Create the core unit
Synthesize it in Quartis
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

8. Copyright 2012 - Joanne DeGroat, ECE, OSU
Assignment HW 13
Complete the ALU unit.
Add the remaining internal muxes and internal control unit that given the operation input, generates the internal control signals.
Note that for an increment it is easy to simply add one to the A input. For decrement add FF (-1) to the A input. (3-1=2 : =0010, 6-1 : =0101)
Once this is complete and synthesizes OK, add input registers and an output driver to give the unit shown in the datapath.
9/2/2012 – ECE 3561 Lect 9
Copyright Joanne DeGroat, ECE, OSU

9. Copyright 2012 - Joanne DeGroat, ECE, OSU
Assignment 14
This is the final assignment
Integrate the ALU with the register to form a datapath.
Synthesize it to synthesize a complete datapath. Write a report that includes the HDL code, the RTL diagram from synthesis, and the basic synthesis statistics.
Simulate it to load values into the register. You will need to simulate two logic operations, an add, an increment, and a decrement. For these show the simulation cycle where the data is sent to the ALU and the simulation cycle where the result is returned to the register. Be sure the show the busses, and the control signals on the simulation waveform and explain them in the text of the report.
9/2/2012 – ECE 3561 Lect 9
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