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Pipelined Implementation : Part I

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1 Pipelined Implementation : Part I
Seoul National University Pipelined Implementation : Part I

2 Overview General Principles of Pipelining
Seoul National University Overview General Principles of Pipelining Goal Difficulties Creating a Pipelined Y86 Processor Rearranging SEQ Inserting pipeline registers Problems with data and control hazards

3 Real-World Pipelines: Car Washes
Seoul National University Real-World Pipelines: Car Washes Sequential Parallel Pipelined Idea Divide process into independent stages Move objects through stages in sequence At any given times, multiple objects being processed

4 Computational Example
Seoul National University Computational Example Combinational logic R e g 300 ps 20 ps Clock Delay = 320 ps Throughput = 3.12 GIPS System Computation requires total of 300 picoseconds Additional 20 picoseconds to save result in register Must have clock cycle of at least 320 ps

5 3-Way Pipelined Version
Seoul National University 3-Way Pipelined Version R e g Clock Comb. logic A B C 100 ps 20 ps Delay = 360 ps Throughput = 8.33 GIPS System Divide combinational logic into 3 blocks of 100 ps each Can begin new operation as soon as previous one passes through stage A. Begin new operation every 120 ps Overall latency increases 360 ps from start to finish

6 Pipeline Diagrams Unpipelined 3-Way Pipelined
Seoul National University Pipeline Diagrams Unpipelined Cannot start new operation until previous one completes 3-Way Pipelined Up to 3 operations in process simultaneously OP1 Time OP2 OP3 OP1 Time A B C OP2 OP3

7 Operating a Pipeline Clock Comb. logic A B C 100 ps 20 ps 359 100 ps
Seoul National University Operating a Pipeline R e g Clock Comb. logic A B C 100 ps 20 ps 359 R e g 100 ps 20 ps Comb. logic A B C Clock 300 R e g Clock Comb. logic A B C 100 ps 20 ps 239 R e g Clock Comb. logic A B C 100 ps 20 ps 241 Time OP1 OP2 OP3 A B C 120 240 360 480 640 Clock

8 Limitations: Nonuniform Delays
Seoul National University Limitations: Nonuniform Delays R e g Clock Comb. logic B C 50 ps 20 ps 150 ps 100 ps Delay = 510 ps Throughput = 5.88 GIPS A Time OP1 OP2 OP3 A B C Throughput limited by slowest stage Other stages sit idle for much of the time Challenging to partition system into balanced stages

9 Limitations: Register Overhead
Seoul National University Limitations: Register Overhead Delay = 420 ps, Throughput = GIPS Clock R e g Comb. logic 50 ps 20 ps As try to deepen pipeline, overhead of loading registers becomes more significant Percentage of clock cycle spent loading register: 1-stage pipeline: 6.25% 3-stage pipeline: % 6-stage pipeline: % High speeds of modern processor designs obtained through very deep pipelining

10 Data Hazards (Dependencies) in Processors
Seoul National University Data Hazards (Dependencies) in Processors 1 irmovl $50, %eax 2 addl %eax , %ebx 3 mrmovl 100( %ebx ), %edx Result from one instruction used as operand for another Read-after-write (RAW) dependency Very common in actual programs Must make sure our pipeline handles these properly Get correct results Minimize performance impact

11 SEQ Hardware Stages occur in sequence
Seoul National University SEQ Hardware Stages occur in sequence One operation in process at a time

12 SEQ+ Hardware PC Stage Processor State Still sequential implementation
Seoul National University SEQ+ Hardware Still sequential implementation Reorder PC stage to put at beginning PC Stage Task is to select PC for current instruction Based on results computed by previous instruction Processor State PC is no longer stored in register But, can determine PC based on other stored information

13 Adding Pipeline Registers
Seoul National University Adding Pipeline Registers Instruction memory PC increment CC ALU Data Fetch Decode Execute Memory Write back icode ifun rA , rB valC Register file A B M E valP srcA srcB dstA dstB valA valB aluA aluB Cnd valE Addr , Data valM newPC ,

14 Pipeline Stages Fetch Decode Execute Memory Write Back
Seoul National University Pipeline Stages Fetch Select current PC Read instruction Compute incremented PC Decode Read program registers Execute Operate ALU Memory Read or write data memory Write Back Update register file

15 PIPE- Hardware Forward (Upward) Paths
Seoul National University PIPE- Hardware Pipeline registers hold intermediate values from instruction execution Forward (Upward) Paths Values passed from one stage to next Cannot jump over other stages e.g., valC passes through decode

16 Signal Naming Conventions
Seoul National University Signal Naming Conventions S_Field Value of Field held in stage S pipeline register s_Field Value of Field computed in stage S

17 Feedback Paths Predicted PC Branch information Return point
Seoul National University Feedback Paths Predicted PC Guess value of next PC Branch information Jump taken/not-taken Fall-through or target address Return point Read from memory Register updates To register file write ports

18 Seoul National University
Predicting the PC Start fetch of new instruction after current one has completed fetch stage Not possible to determine the next instruction 100% correctly Guess which instruction will follow Recover if prediction was incorrect

19 Our Prediction Strategy
Seoul National University Our Prediction Strategy Instructions that Don’t Transfer Control Predict next PC to be valP Always reliable Call and Unconditional Jumps Predict next PC to be valC (destination) Conditional Jumps Only correct if branch is taken Typically right 60% of time Return Instruction Don’t try to predict

20 Recovering from PC Misprediction
Seoul National University Recovering from PC Misprediction Mispredicted Jump Will see branch condition flag once instruction reaches memory stage Can get fall-through PC from valA (value M_valA) Return Instruction Will get return PC when ret reaches write-back stage (W_valM)

21 Pipeline Demonstration
Seoul National University Pipeline Demonstration irmovl $1,%eax #I1 1 2 3 4 5 6 7 8 9 F D E M W irmovl $2,%ecx #I2 irmovl $3,%edx #I3 irmovl $4,%ebx #I4 halt #I5 Cycle 5 I1 I2 I3 I4 I5

22 Data Dependencies: No Nop
Seoul National University Data Dependencies: No Nop 0x000: irmovl $10,% edx 0x006: $3,% eax 0x00c: addl % ,% 0x00e: halt 1 2 3 4 5 6 7 8 F D E M W valA f R[ % edx ] = valB eax Cycle 4 Error M_ valE = 10 dstE e_ 0 + 3 = 3 E_

23 Data Dependencies: 1 Nop
Seoul National University Data Dependencies: 1 Nop 0x000: irmovl $10,% edx 0x006: $3,% eax 0x00c: nop 0x00d: addl % ,% 0x00f: halt 1 2 3 4 5 6 7 8 9 F D E M W R[ % edx ] f 10 valA = valB eax • Cycle 5 Error M_ valE = 3 dstE

24 Data Dependencies: 2 Nop’s
Seoul National University Data Dependencies: 2 Nop’s 0x000: irmovl $10,% edx 0x006: $3,% eax 0x00c: nop 0x00d: 0x00e: addl % ,% 0x010: halt 1 2 3 4 5 6 7 8 9 10 F F D D E E M M W W F F D D E E M M W W F F D D E E M M W W F F D D E E M M W W F F D D E E M M W W F F D D E E M M W W D valA f R[ % edx ] = 10 valB eax • Cycle 6 Error W R[ % eax ] f 3 W W R[ R[ % % eax eax ] ] f f 3 3 • • • D valA f R[ % edx ] = 10 valB eax

25 Data Dependencies: 3 Nop’s
Seoul National University Data Dependencies: 3 Nop’s 0x000: irmovl $10,% edx 0x006: $3,% eax 0x00c: nop 0x00d: 0x00e: 0x00f: addl % ,% 0x011: halt 1 2 3 4 5 6 7 8 9 F D E M W 10 R[ ] f valA = valB Cycle 6 11 Cycle 7

26 Branch Misprediction Example
Seoul National University Branch Misprediction Example 0x000: xorl %eax,%eax 0x002: jne t # Not taken 0x007: irmovl $1, %eax # Fall through 0x00d: nop 0x00e: nop 0x00f: nop 0x010: halt 0x011: t: irmovl $3, %edx # Target (Should not execute) 0x017: irmovl $4, %ecx # Should not execute 0x01d: irmovl $5, %edx # Should not execute

27 Branch Misprediction Trace
Seoul National University Branch Misprediction Trace 1 2 3 4 5 6 7 8 9 F D E M W Cycle 5 valE f dstE = % edx M_Cnd = M_ valA = 0x007 valC ecx rB eax 0x000: xorl % eax ,% eax 0x002: jne t # Not taken ... 0x011: t: irmovl $3, % edx # Target 0x017: irmovl $4, % ecx # Target+1 0x007: irmovl $1, % eax # Fall Through Incorrectly execute two instructions at branch target

28 Return Example 0x000: irmovl Stack,%esp # Initialize stack pointer
Seoul National University Return Example 0x000: irmovl Stack,%esp # Initialize stack pointer 0x006: nop # Avoid hazard on %esp 0x007: nop 0x008: nop 0x009: call p # Procedure call 0x00e: irmovl $5,%esi # Return point 0x014: halt 0x020: .pos 0x20 0x020: p: nop # procedure 0x021: nop 0x022: nop 0x023: ret 0x024: irmovl $1,%eax # Should not be executed 0x02a: irmovl $2,%ecx # Should not be executed 0x030: irmovl $3,%edx # Should not be executed 0x036: irmovl $4,%ebx # Should not be executed 0x100: .pos 0x100 0x100: Stack: # Stack: Stack pointer

29 Incorrect Return Example
Seoul National University Incorrect Return Example F D E M W valE f 2 dstE = % ecx 1 eax valC 3 edx 5 rB esi valM 0x0e 0x024: irmovl $1,% # Oops! 0x02a: $2,% 0x030: $3,% 0x00e: $5,% 0x023: ret # Return Incorrectly execute 3 instructions following ret

30 Pipeline Summary Concept Limitations Fixing the Pipeline
Seoul National University Pipeline Summary Concept Break instruction execution into 5 stages Run instructions through in pipelined mode Limitations Can’t handle dependencies between instructions when instructions follow too closely Data dependencies One instruction writes register, later one reads it Control dependency Instruction sets PC in way that pipeline did not predict correctly Mispredicted branch and return Fixing the Pipeline We’ll do that next time

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