1. Week 10, Finite State Machine
Introduction to Digital System and Microprocessor Design
Wonju Seo, Taesu Kim
April 25, 2017
Slides made by Daehyun Ahn, DICE

2. In case of Mealy Machine
Finite State Machine
State register
Output logic
Next state logic
Input
Output
In case of Mealy Machine
CLK
RST

3. FSM Example: 2-bit up-down counter

4. 2-bit up-down counter code
Define states as parameters
State register
Output logic & next state logic

5. 2-bit up-down simulation result

6. Exercise: Digital Clock with simple FSM
Edit hour
(Stop clock)
Hour switch on
Up switch on
Down switch on
Edit second
Edit minute
Min switch on
Sec switch on
Hour switch off
Min switch off
Sec switch off
Add a time-editing function to last week’s digital clock. (Use your last week’s digital clock code)
When up switch is on, increases hour/min/sec by 1 for 1 second. (When hour is 23 or min/sec is 59, return 0)
When down switch is on, decreases hour/min/sec by 1 for 1 second. (When hour/minute/sec is 0, return 23 or 59)
When it is in time-editing mode, the clock should stop.
You can ignore abnormal conditions (ex: both hour and min switches are on, both up and down switches are on, ……)
Initialize time to 19:55:50
Input: 3 switches for time-editing (hour, min, sec), 2 switches for up/down, clk_ms
Output: [7:0] seg_out, seg_com
Return button

7. I/O Pin Planning Switch1 Xilinx Switch2 1 W15 AD12 2 AA13 AC11 3 AF134
AD15
W13 5
AE15
Y13 6
AA15
AE12 7
AB15
AF12 8
Y16
AB14
9/9

8. I/O Pin Planning Seg_out Xilinx Seg_com A AF5 #1 AD2 B AE5 #2 W2 C AB6#3 W1 D
AA6 #4
AB4 E
K26 #5
AB3 F
K25 #6 W6 G
AC2 #7 W5 DP
AC1 #8 W4
Clk
A13
9/9