1. Introduction to Micro Controllers & Embedded System Design
Department of Electrical & Computer Engineering Missouri University of Science & Technology
A.R. Hurson

2. Stored Program Machine: A computer with a storage component that may contain both data to be manipulated and instructions to manipulate the data is called a stored program machine. This simply implies that the user is able to change the sequence of operations on the data.
Program: The sequence of operations performed on the data is called a program. More formally, it is a finite set of instructions that specify the operands, operations, and the sequence by which processing has to occur.
A.R. Hurson

3. Instruction: An instruction is a group of bits that tells the computer to perform a specific operation. It is composed of two parts:
Operation part
Operand part
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4. Operation part (operation code) is a group of bits that defines the action to be performed.
For each machine the set of operations is limited and defined.
In general, a machine with n bits as op.code is capable of supporting 2n distinct operations each having a distinct encoding as op.code.
A.R. Hurson

5. Operand part defines the element (s) needed for operation.
Within the scope of a program, besides the op.code, one needs four pieces of information (note majority of operations are binary operations):
2 operands as sources
1 operand as a destination
1 operand to specify the location of the next instruction that should be fetched.
A.R. Hurson

6. Depending on how many of these pieces of information are explicitly defined, instructions are grouped into 5 classes: 4, 3, 2, 1, and 0-address instructions.
A.R. Hurson

7. Register addressing
In 8051 programmer has access to eight “working registers” numbered R0 to R7.
Three least significant bits of op.code are used to specify a register.
The 8051 assembly language indicates register addressing with the symbol Rn (0  n  7).
A.R. Hurson

8. Instruction format Register addressing Op.code Register Example
ADD A, R7 
register
Op.code
Op.code
Register
Instruction format
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9. Implied
Some instructions are referring to specific register such as A (accumulator), DPTR (data pointer), PC (program counter), and B register so address bits are not needed. In another words, op.code indicates the register involved in the operation.
Example
INC DPTR
MUL AB
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10. Instruction format Direct addressing Op.code Direct addressing
Direct addressing allows access to any on-chip variable or hardware register. An additional byte is appended to the op.code specifying the location to be used.
Example
MOV P1, A
Op.code
Direct addressing
Instruction format
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11. Indirect addressing
In 8051, R0 and R1 may operate as a “pointer” register. In this case, the low order bit of op.code indicates which register.
In 8051assembly language, indirect addressing is identified as preceding either R0 or R1.
A.R. Hurson

12. Instruction format Indirect addressing i Op.code
Example: Assume R1 contains 40H and internal memory address 40H contains 55H, then the instruction
MOV
moves 55H into the accumulator i
Op.code
R0 or R1
Instruction format
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13. Instruction format Immediate addressing Op.code Immediate data
In assembly language of 8051, immediate addressing is identified by “#” symbol. The operand may be a numeric constant, a symbolic variable, or an arithmetic expression using constant, symbols, and operators. Assembler calculates the expression and substitutes the result into the instruction.
Op.code
Immediate data
Instruction format
A.R. Hurson

14. Immediate addressing Example: MOV A, #12
Note: There is just one exception when initializing the data pointer, we need a 16-bit constant, therefore
MOV DPTR, #8000H is a 3-byte instruction with a 16-bit constant 8000H.
A.R. Hurson

15. Instruction format Relative addressing Op.code Relative offset
This addressing mode is used with certain jump instructions. A relative address is an 8-bit signed value which is added to the contents of the program counter to form address of the next instruction to be fetched and executed.
Naturally, the range for jump is -128 to +127 locations.
Op.code
Relative offset
Instruction format
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16. Relative addressing
Example: Assume label THREE represents an instruction at location 1040H and instruction
SJMP THREE is in memory location 1000H and H, then the assembler assigns a relative offset of 3EH as byte-two of the instruction since
1002H + 3EH = 1040H
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17. Instruction format Absolute addressing Op.code A7-A0
Absolute addressing is just used with ACALL and AJMP instructions. These 2-byte instructions allow branching within the current 2K page of code memory by providing the 11 least significant bits of destination address in op.code (i.e., A10-A8 and byte 2 of instruction A7-A0).
A10-A8
Op.code
A7-A0
Instruction format
A.R. Hurson

18. Absolute addressing
The upper five bits of the destination address are the current value of the upper five bits of program counter. Therefore, the next instruction after the branch and the destination instruction must be within the same 2K page.
A.R. Hurson

19. PC or DPTR + ACC = effective address
Index addressing
Index addressing uses a base register (either the program counter or the data pointer) and an offset (the accumulator) in forming the effective address for JMP or MOVC instructions.
Example: MOVC
PC or DPTR + ACC = effective address
Base register
Offset
A.R. Hurson