1. Types of Amplifiers Common source, input pairs, are transconductance
Most whole CMOS op amps are transconductance
Common gate can be viewed as current amplifier
Current mirrors are current amplifier
Common drain or source follower is voltage amplifier
Can cascade two or more basic one to get new types

2. Single transistor amplifiers, building blocks
Rin =
Rout =
Rin =
Rout =
Rin =
Rout =

3. Analysis of amplifiers
DC analysis
Find DC operating points, i.e., quiescent point, or Q point
Finding the quiescent voltages VXXQ’s at various nodes
Finding IXXQ’s through various branches
Large signal static analysis
Plot of output versus input (transfer curve)
Large signal gain
Output and input swing limits
Small signal static and AC analysis
DC gain A0, AC gain A(s)
Input resistance/impedance, output resistance/impedance
Small signal dynamic analysis
Bandwidth, overshoot, settling
Noise
Power supply rejection
Large signal dynamic analysis
Slew rate
Nonlinearity

4. Simple Inverting Amplifiers

5. Common source with diode load
vOUT
VDD
|VTP|
M1/2 sat
vodP
VGS-VTN
M1 cutoff
M2 sat
vodN
M1 tiode
M2 sat
vIN
VDD
VTN
ID = ½bP(VDD-vOUT -|VTP|)2(1+lP(VDD-vOUT)) = ½bN(vIN-VTN)2(1+lNvOUT)

6. Large signal limits Absolute limits: None for v_in
v_out: v_out at Vin=VDD to VDD-VTP
To have all transistors in saturation:
Vin range:
Vout range:

7. Small Signal Characteristics
Inverter with diode connection load
Small Signal Characteristics

8. High gain inverters

9. Current source load or push-pull
Refer to book for large signal analysis
Must match quiescent currents in PMOS and NMOS transistors
Wider output swing, especially push-pull
Much higher gain (at DC), but much lower -3dB frequency (vs diode load)
About the same GB
Very power dependent

10. Small signal
High gain! Especially at low power.

11. Dependence of Gain upon Bias CurrentID ID + - Vg
Vo+D + - Vg Vo

13. Use sufficient gm/Id
Use sufficient L
Use sufficient Vds-Ex

14. 3 ways to increase A0: larger L, sufficient VDS, and small current density.
But:
Larger L reduces fT, slows down operation.
VDS freedom is limited: in the 2nd stage VDS range is larger but must meet Vo swing requirement; 1st stage VDS range is quite small.
Small current density also leads to slow operation.

15. Key to analysis by hand:
Use level 1 or 3 model equations
Use KCL/KVL

17. Transfer function of a system
input u
output y
System
zeros
poles

18. For stability All closed loop poles must have negative real parts
But open loop poles do not need to be stable
Feedback changes the location of the poles
Location of zeros cannot be changed by feedback
Right half plane zeros do not cause instability by themselves
But they have very negative impact on phase margin, making stabilization more difficult

19. Nodal analysis Identify nontrivial nodes Write a KCL at each node
Solve for TF from input to output

20. Frequency Response of CMOS Inverters
Only one non trivial node
KCL:
YtotVout(s)=Iinj
Ytot =gds1+gds2+sCgd1
+sCBD1+sCL+sCBD2
+sCGD2
=go+sCL’
Iinj=-gm1vin+sCGD1vin

22. CMOS Inverters Let x=vin Still only one non trivial node KCL:
YtotVout(s)=Iinj
Same Ytot =gds1+gds2+sCgd1
+sCBD1+sCL+sCBD2
+sCGD2
=go+sCL’
But Iinj=-gm1vin+sCGD1vin –gm2vin+sCGD2vin

24. Input output transfer function
When s=jw0, A(0) 
When w∞, A(s)

25. Unity gain frequency of
Loop gain Ab
=-3dB frequency of closed loop
=b*GB
gain
|A0 | =gm/go
Acl=1/b
0 dB
BW:
|p1|=
g0/CL’
gain BW
product
=|A0p1|
=GB
=gm/CL’
|z1|
=gm/Cgd
=GB*CL’/Cgd

26. Feedback changed pole location, but does not change zero location.
Unity gain feedback
A(s)
Closed-loop zero: z1
Feedback changed pole location, but does not change zero location.

27. If a step input is given, the output response is
By the final value theorem:
By the initial value theorem:

28. Right half plane zero causes initial reverse transient, whose size depends on main pole/zero ratio.-1
Final settling determined by A0
 need high gain
Settling speed determined by A0p1=GB=UGF,
 need high gain bandwidth product

29. Gain bandwidth product
C’L = Ctotal = CGD1+ CGD2+ CBD1+ CBD2+ CL
If fixed VEB used, W, ID, gm increase in proportion; GB initially increases but saturates near C’L=2CL.

30. Gain bandwidth product: ID bias

31. For small CL
GB0 W1

32. At max GB sizing Use large current density Use small L
Use NMOS for larger m
Use smallest drain area
Use larger VD
Large Cox: thin oxide and high K
Small gate drain overlap DL, small side wall capacitance density

33. Max GB and slew rate

34. NOISE IN MOS INVERTERS

35. To minimize:
L2 >>L1
en1 small

38. For thermal noise