Testability of Multi-Level Circuits

Testability of Multi-Level Circuits
Sungho Kang Yonsei University

Outline Introduction Single Stuck-At Faults
Equivalent Normal Form Representation ENF Reducibility ENF Reducibility Preserving Transforms Hazard Free Robust Path Delay Faults General Robust Path Delay Faults Hazard Free Robust Gate Delay Faults Hazard Free Robust Stuck-Open Faults

Introduction Introduction To facilitate testability analysis for multiple stuck at faults and delay faults, equivalent normal form(ENF) is used which is the two level representation of multilevel circuits

Conditions for Testability
Single Stuck-at Faults

Boolean Difference Single Stuck-at Faults

Boolean Difference Example
Single Stuck-at Faults

Boolean Difference Single Stuck-at Faults

Boolean Difference : Example
Single Stuck-at Faults Test for fault G2 s-a-0

Test Generation : D Single Stuck-at Faults Introduce D and D’

Test Generation : PODEM
Single Stuck-at Faults Path Oriented DEcision Making Search space on PIs Implicit space enumeration Algorithm PODEM() if (Error at PO) return SUCCESS if (test not possible) return FAILURE get an objective backtrace the objective to PI imply the PI value if PODEM() == SUCCESS imply PI with X value assume target fault is I s-a-v objective() if ( the value of I is X ) return (I, v’) select a gate(G) from the D frontier select an input j of G with value X c = controlling value of G return ( j, c’)

Don’t Cares and Testability
Single Stuck-at Faults A Boolean network can be made prime and irredundant by minimizing each node in the network under its complete observability and satisfiability don’t care sets, where each node is a two-level Boolean function A signal yj can be tested for s-a-1 by finding an input vector V such that V is contained in both SDC’yj’ and ODC’y 1st term : When we evaluate the network at V the value of yj is 0 and the other values of the intermediate variables yi satisfy the compatibility relations yi = f(V,y) 2nd term : the value of V is such that it allows the value of yj to be observed at least at one output Redundancy removal If a signal yj is not testable for s-a-1 (s-a-0) then the network is unaffected form a logical functionally standpoint if yj is replaced with 1 (0) thereby simplifying network

Don’t Cares and Testability
Single Stuck-at Faults The most popular method for obtaining prime and irredundant networks or fully single stuck-at testable multilevel circuits is to use test generation algorithms to iteratively identify ad remove single stuck-at fault redundancies in combinational logic circuits

Performance and Testability
Single Stuck-at Faults Redundancy removal improves testability and reduces the area of a circuit There are circuits where removing the stuck at fault redundancy affetcts the speed adversely

Single Stuck-at Faults Fully single stuck-at fault testable obtained by applying the speed-maintaining redundancy removal algorithm Replacing the connection from the output of gate 7 to gate 9 by the PI b0

Single Stuck-at Faults A redundancy removal procedure that maintains the speed of a circuit, but can increase the area of a circuit If the longest path is not statically sensitizable, then the path is made fanout free In most cases, the longest paths are statically sensitizable and straightforward redundancy removal procedures can be applied

Single Stuck-at Faults Replace the marked wire with a constant 0 The longest path is statically sensitizable

Single Stuck-at Faults The marked s-a-1 redundancy is removed

ENF Representation ENF Representation ENF is a two-level representation in which the sensitization conditions for each path are represented by a cube with each literal in the cube annotated by information regarding its path from the PI to PO

More Formal ENF Definition
ENF Representation Example : Multilevel circuit

ENF Representation Making a circuit internal fanout free

ENF Representation Pushing inverters to the PIs

ENF Representation A two-level circuit representing the ENF

ENF Representation ENF Representation The primary motivation for using the ENF to describe the necessary and sufficient conditions for testability is for clarity of exposition and for the case of proving that synthesis procedures retain testability ENF analysis is only used in proofs An input assignment that sensitizes a 1 along a path need not statically sensitize a 1 along a path The condition for statically sensitizing a 1 is stronger than sensitizing a 1

ENF Reducibility ENF Reducibility Two cubes c and d are syntactically identical (c  s d) if and only if they are equal as sets of literals Two SOPs C and D are syntactically identical (C  s D) if and only if they are equal as sets of cubes An ENF expression E, considered as an untagged SOP expression is denoted NOTAGS(E) Two ENF expression E and F are syntactically identical up to a remaining of tags denoted E  t F if and only if NOTAGS(E)  s NOTAGS(F) and there is a many-to-one mapping from the tagged literals of E to the tagged literals of F This property of ENF equivalence up to a many-to-one mapping of tags : ENF reducibility

Resubstitution without Complement
Preserving Transforms Let be a Boolean network  of N nodes, and for one node k in  let Fk = G+HC where G, H, and C are covers and H and C have no variables on common Let ’ be a Boolean network of N+1 nodes obtained by factoring C from Fk In other words, for 1iN, ik, F’i = Fi Let the new node be F’N+1=C with associated output variable y’N+1 and let F’k =G+Hy’N+1 Then the ENF expression of  is related to the ENF expression of ’ by E  t E’

Resubstitution without Complement
Preserving Transforms Let be a Boolean network  of N nodes, and let Fj = C and Fk = C, where C is a cover, be two nodes in  Let ’ be a Boolean network of N-1 with Fj =resubstituted for Fk In other words, for 1iN-1, ik, let F’i = Fi, except let all instances of literal yk in F’i be replaced by instances of literal yj Then the ENF expression of , E, is syntactically identical up to a renaming of tags to the ENF expression of ’, E’ Let C be a single-output combinational circuit with ENF expression EC Let M be C after the resubstitution of a single uncomplemented algebraic factor Then EC  t E7M

Resubstitution with Complement
Preserving Transforms Let be a Boolean network  of N nodes, and for one node k in  let the cover of Fk be G Let ’ be a Boolean network of N+1 nodes obtained by pushing an inverter out from Fk In other words, for 1iN, ik, F’i = Fi Let the new node be F’N+1 = y’k and let F’k =G’ If when the node F’k and ’ is collapsed into node F’N+1 the resulting cover is syntactically identical to the node Fk in , then the ENF expression of  is syntactically identical up to a remaining of tags to the ENF expression of ’

Resubstitution with Complement
Preserving Transforms Let C be a single-output combinational circuit with ENF expression EC Let M be C after the resubstitution of a single uncomplemented algebraic factor as constrained by the lemma in the previous page Then EC  t E7M

Technology Mapping Preserving Transforms Let C be a NAND gate and INVERTER implementation of a circuit, and let M be a tree covering based technology mapped version of C A vector sequence <V1, V2> event sensitizes a path P in C if and only if <V1, V2> event sensitizes the corresponding path Q in M

Nonretainment of ENF Reducibility
Preserving Transforms Eliminating a node by pushing it into its fanout nodes can destroy ENF reducibility Modifying the cover of any node in a Booean network necessarily changes the ENF expression and therefore does not retain ENF reducibility

HFR Path Delay Faults Given a circuit C with ENF expression E and a tagged literal L, the path-cube-complex associated l is the set of al cubes q such that l  q and there is no other tagged literal m  q Let C be a multilevel single-output circuit with ENF E Let P be a path in C and let the tagged literal associated with P be l Let the path-cube-complex of l be L and let D be those cubes not containing l If <V1, V2> is a hazard free robust path delay fault test for P in C, then for every cube d in D there exists some literal m in both V1 and V2 such that dm(V1)=0 and dm(V2)=0

HFR Path Delay Faults Let C be a multilevel single-output circuit with ENF E Let P be a path in C and let the tagged literal associated with P be l Let the path-cube-complex of l be L and let D be those cubes not containing l There exists a hazard free robust path delay fault test for P in C if and only if all the following three conditions are met There exists a vertex V2 such that L(V2)=1 and V2 is not covered by any cube in D There exists a vertex V1=V2-{l}{l’} such that V1 is in the OFF-set of C For every cube d in D there exists some literal m in both V1 and V2 such that dm(V1)=0 and dm(V2)=0

Test Generation Methods
HFR Path Delay Faults The I-edge of a path P with input l in a leaf-DAG is the fitst connection of P after an inverter, if it exits The I-edge is said to be associated with input l Let P be a path starting with PI l in a leaf-DAG L Let Por (Pand) be the set of paths which pass through side-inputs to all the OR (AND) gates along P, such that the I-edge of each Q  Por (Q  Pand) is associated with input l The smooth circuit for path P is obtained by replacing the I-edge of each Q  Por by 1 and each Q  Pand by 0

HFR Path Delay Faults Let P be a path in a leaf-DAG L <V1, V2> is a hazard-free robust delay fault test for P in the smooth circuit Ls if and only if <V1, V2> is a hazard free robust path delay fault test for P in L Let P be a path with input l in a leaf-DAG L V2 is a test for the s-a-0 fault on the I-edge of P in the smooth network Ls for P if and only if <V1, V2>, where V2=V2-{l}{l’}, is a hazard-free robust delay fault test for the rising transition on P in L

More Efficient Procedures
HFR Path Delay Faults Consider N* which is obtained form a multilevel circuit N by pushing all inverters in N to the PIs The inverter at the output of a gate may be moved to the inputs by using DeMorgan’s laws of complementation All inverters may be moved to the PIs by starting at the POs and recursively applying this procedure to all gates N* is at most twice the size of N The only other step we need to perform is to make the path P beginning from input l in N* for which we want to generate a delay fault test fanout-free after l This entails duplicating the fates on P at most once and results in a N*P which is at most four times the size of N The number of inputs is the same as that of N, making this method more efficient than the methods that use multivalued logic Given N*P we can construct the smooth network N*S for P by replacing the appropriate I-edges associated with l by 1 and 0 Since N*P is inversion free after the PIs, each I-edge associated with ii either converges with P at an OR gate or an AND gate

Synthesis for Full Testability
HFR Path Delay Faults Let C be a single-output circuit with ENF expression EC Let M be a single-output circuit with ENF expression EM If EC  EM and if a vector set V hazard-free robustly detects all path delay faults in C, then V hazard-free robustly detects all path delay faults in M Algebraic factorization can improve the HFRPDF testability of a circuit C = ab’+b’c+bc’ M= (a+c)b’+bc’ The path associated with b’ in cube ab’ is not HFRPDF testable After C is factored into M, a single path with b’ is testable M is completely HFRPDF testable

HFR Path Delay Faults ENF reducibility does not imply the preservation of hazard-free robust gate delay fault(HFRGDF) testability The conditions for HFRGDF testability are weak and require a stronger form of ENF reducibility Given a completely hazard-free robust path delay fault testable network, algebraic factorization with a constrained use of the inverse produces a completely hazard-free robust delay fault testable network

HFR Path Delay Faults Algebraic factorization without the constraint embodied by the following lemma may result in a circuit which is not HFRPDF testable Lemma :Let be a Boolean network  of N nodes, and for one node k in  let the cover of Fk be G; Let ’ be a Boolean network of N+1 nodes obtained by pushing an inverter out from Fk ; In other words, for 1iN, ik, F’i=Fi ; Let the new node be F’N+1 = y’k and let F’k =G’; If when the node F’k and ’ is collapsed into node F’N+1 the resulting cover is syntactically identical to the node Fk in , then the ENF expression of  is syntactically identical up to a remaining of tags to the ENF expression of ’

HFR Path Delay Faults This phenomenon is related to the fact that if the constraint is not satisfied, the number of paths may increase after factorization Example : multilevel circuit that is completely HFRPDF testable

HFR Path Delay Faults Example multilevel circuit that is completely HFRPDF testable after factorization using the complement procedure, path {c’, 2, 6, 0, 7, 10} is not HFR testable

Techniques for Full Testability
HFR Path Delay Faults If C1 and C2 are hazard-free robust path delay fault testable combinational circuit, the input variables of C1 and C2 are disjoint, and a circuit C is created by connecting one output oj of C1 to one input ik of C2, then C is also hazard-free robust path delay fault testable A single path starting with input ik of C2 is not hazard-free robust path delay fault testable, then all the paths in the subcircuit C1 may be untestable in C

HFR Path Delay Faults If P is parity tree built form XOR gates that are logically and topologically equivalent to those in the dotted box in the below figure, then P is hazard-free robust path delay fault testable

HFR Path Delay Faults If A is a ripple-carry adder built from full adders that are logically and topologically equivalent to that in the below figure, then A is hazard-free robust path delay fault testable

Shannon Decomposition
HFR Path Delay Faults Given two hazard-free robust path delay fault testable circuits C1 and C2 whose inputs are x1, …, xN, if the outputs of C1 and C2 are connected to a multiplexor with a control input xN+1, the if the composition C is fully single stuck-at fault testable, C is fully hazard-free robust path delay testable

Shannon Decomposition
HFR Path Delay Faults Method to produce a completely HFRPDF testable realization of a function f Minimize f to produce a prime and irredundant two-level logic circuit Check if the path delay faults in the two-level function f are testable; If yes, stop here Identify the product terms associated with the paths that are not robustly testable; Select a binate input variable xi that is an input to the maximum number of the identified product terms Cofactor f with respect to xi; Apply the procedure to fxi and fxi’ f is implemented as xifxi + xi’fxi’ A multiplexor-based network , where no input is encountered more than once along any path from inputs of the circuit to the output, is fully hazard-free robust path delay fault testable if it is fully single stuck-at fault testable

Robust Path Delay Faults Let C be a multilevel single-output circuit with ENF E Let P be a path in C and let the tagged literal associated with P be l Let the complete path-cube-complex of l be L and let D be those cubes not containing l There exists a general robust delay fault test for a rising transition on P in C if and only if all the following three conditions are met There exists a vertex V2 such that L(V2) =1 and V2 is not covered by any cube in D There exists a vertex V1=V2-{l}{l’} such that V1 is in the OFF-set of C For every cube d in D there exists some literal m in both V1 and V2 such that dm(V1)=0 and dm(V2)=0

Robust Path Delay Faults Let C be a multilevel single-output circuit with ENF E Let P be a path in C and let the tagged literal associated with P be l Let the path-cube-complex of l be L and let D be those cubes not containing l There exists a general robust delay fault test for a falling transition on P in C if and only if all the following two conditions are met There exists a vertex V1 such that L(V2) =1 There exists a vertex V2=V1-{l}{l’} such that V2 is in the OFF-set of C

Test Generation Let P be a path starting with PI l in a leaf-DAG L
Robust Path Delay Faults Let P be a path starting with PI l in a leaf-DAG L Let Por (Pand) be the set of paths which pass through side-inputs to all the OR (AND) gates along P, such that the I-edge of each Q  Por (Q  Pand) is associated with input l The rising smooth (falling smooth) circuit for path P is obtained by replacing the I-edge of each Q  Por by 1 and each Q  Pand by 0

Test Generation Let P be a path in a leaf-DAG L
Robust Path Delay Faults Let P be a path in a leaf-DAG L <V1, V2> is a GRPDF test for rising transition on P in the rising smooth circuit LR if and only if <V1, V2> is a GRPDF test for the rising transition on P in L Let P be a path with input l in a leaf-DAG L V2 is a test for the s-a-0 fault on the I-edge of P in the rising smooth network LR for P if and only if <V1, V2>, where V2=V2-{l}{l’}, is a GRPDF test for the rising transition on P in L

Robust Path Delay Faults Let C be a single-output circuit with ENF expression EC Let M be a single-output circuit with ENF expression EM If EC  t EM and if a vector set V is a general robust test set for all path delay faults in C, then V is a GRPDF test for all path delay faults in M

HFR Gate Delay Faults The conditions for hazard-free robustly detecting a gate delay fault in a multilevel circuit are simpler to achieve than for hazard-free robustly detecting a path delay fault The gate-cube-complex of a gate g, call it Lg, in a circuit C with ENF E is defined as the set of all cubes containing tagged literals associated with a path through g More formally Lg={q  E| (lP  q)  (g  P)} In the qube q there could be tagged literals lP and lQ such that wither g  P or g  Q, or g in both P and Q

HFR Gate Delay Faults Let C be a multilevel single-output circuit with ENF E Let g be a gate in C and let the gate-cube-complex of g be Lg Let D = E - Lg If <V1, V2> is an HFRGDF test for g in C, then for every cube d in D, there exists some literal m in both V1 and V2 such that dm(V1)=0 and dm(V2)=0

HFR Gate Delay Faults Let C be a multilevel single-output circuit with ENF E and let g be a gate in C There exists an HFRGDF test for gate g in C on a rising primary output transition if and only if there exists some literal l such that all the following four conditions are met There exists a cube q such that q Lg(l), where Lg(l) is the single-literal gate-cube-complex associated with g and l There exists a vertex V2 such that q(V2)=1 and V2 is not covered by any cube in D=E-Lg(l) There exists a literal l  q such that g  P and V1=V2-{l}{l’} is in the OFF-set of C For every cube d in D there exists some literal m in both V1 and V2 such that dm(V1)=0 and dm(V2)=0

HFR Gate Delay Faults A test generation method for gate delay faults that is a simple modification of the path delay fault test generation method is to pick a particular path P that passes through the gate g beginning from input l and attempt to generate an HFRPDF test for P Choose a particular input l that is in the transitive fanin of gate g Attempt to generate <V1, V2> test for gate g that is distance-1 in l If this fails, then pick another input that is in the transitive fanin of g and so on

Algebraic Factorization
HFR Gate Delay Faults It has been observed that more often than not algebraic factorization increases HFRGDF testability f=ab’+a’b+cd’+c’d+a’d a’d is not hazard-free robust testable If f = ab’+cd’+c’d+a’(b+d), it is completely hazard-free robust testable for gate delay faults An algebraic factorization procedure that retains HFRGDF testability of the initial two-level circuit must essentially ensure that in each cube of each factor (cube or kernel) there is at least one literal with the properties of literal l

HFR Gate Delay Faults Given a two-level network C, assume that at least one path through each AND gate is hazard-free robust testable Let EC be the ENF of circuit C Let A be a multilevel circuit resulting from an algebraic factorization of C, having an ENF EA If the tagged literals in EC which satisfy the conditions of Theorem correspond to a set of tagged literals in EA that cover all the gates in A, then A is completely HFRGDF testable Theorem: Let C be a multilevel single-output circuit with ENF E; Let P be a path in C and let the tagged literal associated with P be l ; Let the path-cube-complex of l be L and let D be those cubes not containing l; There exists a hazard free robust path delay fault test for P in C if and only if all the following three conditions are met; There exists a vertex V2 such that L(V2)=1 and V2 is not covered by any cube in D; There exists a vertex V1=V2-{l}{l’} such that V1 is in the OFF-set of C ; For every cube d in D there exists some literal m in both V1 and V2 such that dm(V1)=0 and dm(V2)=0

HFR Gate Delay Faults Let C be a NAND gate and INVERTER implementation of a circuit , and let M be a tree covering technology mapped version of C Then if C was completely hazard-free robust or general robust gate or path delay fault testable, then so is M

HFR Stuck-Open Faults Let C be a multilevel single-output circuit with ENF E Let K be a link in C There exists a hazard-free robust stuck-open fault test for link K in C if and only if there exists some literal l such that all the following four conditions are met There exists a cube q such that q LK(l), where LK(l) is the single-literal link-cube-complex associated with K and l There exists a vertex V2 such that q(V2)=1 and V2 is not covered by any cube in D=E-LK(l) There exists a vertex V1 such that V1=V2-{l}{l’} is in the OFF-set of C For every cube d in D there exists some literal m in both V1 and V2 such that dm(V1)=0 and dm(V2)=0

Synthesis for Testability
HFR Stuck-Open Faults Given ENF reducibility across a multiple-output two-level and a multilevel network, if the two-level network is fully hazard0free robust transistor stuck-open fault testable, then so is the multilevel network Furthermore, the test vectors that hazard free robustly detect all stuck-open faults in the two-level network, hazard-free robustly detect all faults in the multilevel network

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