1. Sequential Logic

2. Types of digital systems
1) Combinational logic circuits :-
2) Sequential logic circuits:-
In Combinational logic circuits, where the output of combination circuit at any instant of time, depends only on the levels present at input terminal.
Combinational logic circuits do not use any memory.
Hence the previous state of input does not have any affect on the present state of the circuit.

3. Sequential Logic Circuits1 7 3
So far we have only considered circuits where the output is purely a function of the inputs
With sequential circuits the output is a function of the values of past and present inputs This particular example is not very useful
Examples of sequential circuits
A counter to count the number of times a signal has changed
A traffic light controller (remembering where it is up to in the sequence)
X = X + A

4. Sequential Circuits - Aims
The output of a sequential circuit depends on the present input & the previous output & the sequence in which the inputs are applied.
In order to provide the previous input or output a memory element is required to be used. Thus a sequential circuit needs memory element.
Also required clock input.
Examples are flip-flops, counter, shift register.

5. Sequential circuit concepts
The addition of a memory device to a combinational circuit allows the output to be fed back into the input:
circuit
Input(s)
Output(s)
memory

6. States
Present state :-the data stored by the memory element at any instant of time is called as the present state i.e Qn,Qn’.
Next state:-the ckt operates on the external inputs and present state to provide new output, new output stored in the memory elements & it is called as next state i.e. Qn+1, Qn+1’.
Clock signal:- it is a timing signal. Its have leading or positive or rising edge & trailing or falling or negative edge.

7. Sequential circuits 1) Synchronous Sequential circuits
2) Asynchronous Sequential circuits
In Synchronous Sequential circuits:-
the state of memory element is affected only if the input changed.
Slower because of the delay.
A clocked flip-flop acts as a memory element.
These circuits are easy to design.

8. In Asynchronous Sequential circuits
The state of memory element will change any time as soon as the input changed.
Faster because clock is not present.
An un-clocked flip-flop or time delay elements acts as a memory element.
These circuits are difficult to design.
LATCH:- the latch is a types of temporary starage device which has two stable states.

9. Synchronous and Asynchronous
circuit
Input(s)
Output(s)
memory
Clock pulse
With synchronous circuits a clock pulse is used to regulate the feedback, input signal only enabled when clock pulse is high – acts like a “gate” being opened.

10. Flip Flops SR Type Flip Flops D Type Flip Flops T Type Flip Flops
J-K Type Flip Flops

11. 1 bit- memory cell or memory elements
A crossed coupled inverter as a memory element
Flip-flop is also known as the basic digital memory circuits. B1
B2 B1 Qn+1
0 0 ?
0 1 0
1 0 1
1 1 Qn Q Q B2
Function Table
Circuit
It has two stable states namely logic 1 and logic 0 state.
The circuit called as cross coupled inverter because the o/p of gate 1 is connected to the input of gate 2 vice versa.

12. operations Assume that the o/p of gate 1, Q=1 hence B2 = 1.
As B2=1 than gate 2 o/p is 0 i.e Q = 0 hennce B1=0.
The o/p of ckt Q & Q will always be complimentary that means Q=1, Q=0, & vice versa.
They will never be qual to Q = Q= 0 OR 1 ia an invalid state.
The ckt has two stable state i.e. Q=1, OR Q= 0 i.e set states, another is Q=0 OR Q= 1i.e. reset states.

13. The Latch SR flip-flop
Modified s-r flip-flops using NAND gates R S Q

14. SR flip-flop using NAND gate
Modified s-r flip-flops using NAND gates
S R Qn Qn c Comments
Case NC NC no change states
Case set state
Case Reset states
Case ? ? Prohibited or invalid states R S Q

15. Latches The SR Latch using NOR gate R R R Q Q Q S S Q Q S Q Symbol
Circuit
Function Table
Although SR LAtch is one of the most important fundamental methods of didgital storage,it is not often used in practice (because of undefined state) - However forms the basis of the more complex latches that we will be dicussing

16. Latches The SR Latch Consider the following circuit R R R Q Q Q S S Q
Symbol
Circuit
R S Qn+1
0 0 Qn
0 1 1
1 0 0
1 1 ?
n+1 represents output at some future time
Function Table
n represents current output.
Although SR LAtch is one of the most important fundamental methods of didgital storage,it is not often used in practice (because of undefined state) - However forms the basis of the more complex latches that we will be dicussing

17. SR Latch operation Assume some previous operation has Q as a 1
Assume R and S are initially inactive
Indicates a stable state at some future time (n+ = now plus)
R = 0
Q = 1
R S Qn+1
0 0 Qn
0 1 1
1 0 0
1 1 ?
~Q = Q, ie is the complement of Q.
S = 0
Q = 0
Circuit
Now assume R goes first to 1 then returns to 0, what happens:

18. Reset goes active
R = 1
When R goes active 1, the output from the first gate must be 0.
Q = 0
This 0 feeds
back to gate 2
S = 0
~Q = 1
Since both inputs are 0 the output is forced to 1
The output ~Q is fed back to gate 1, both inputs being 1 the output Q stays at 0.
R = 1
Q = 0
S = 0
~Q = 1

19. Reset goes in-active
R = 0
Q = 0
When R now goes in-active 0, the feedback from ~Q (still 1), holds Q at 0.
S = 0
~Q = 1
The “pulse” in R has changed the output as shown in the function table:
R S Qn+1
0 0 Qn
0 1 1
1 0 0
1 1 ?
We went from here
To here
And back again
In that process, Q changed from 1 to 0. Further signals on R will have no effect.

20. Set the latch
Similar sequences can be followed to show that setting S to 1 then 0 – activating S – will set Q to a 1 stable state.
When R and S are activated simultaneously both outputs will go to a 0
R = 1
Q = 0
S = 1
~Q = 0
When R and S now go inactive 0, both inputs at both gates are 0 and both gates output a 1.
This 1 fedback to the inputs drives the outputs to 0, again both inputs are 0 and so on and so on and so on and so on.

21. Metastable state
In a perfect world of perfect electronic circuits the oscillation continues indefinitely.
However, delays will not be consistent in both gates so the circuit will collapse into one stable state or another.
R S Qn+1
0 0 Qn
0 1 1
1 0 0
1 1 ?
This collapse is unpredictable.
Thus our function table:
Future output = present output
Set the latch
Reset the latch
Don’t know

22. Latches
The SR Latch
NAND Form produces similar result from inverted inputs R
R S Qn+1
0 0 ?
0 1 0
1 0 1
1 1 Qn Q R R Q Q Q S S S Q Q
Function Table
Circuit
Symbol
You ought to be able to figure this one out yourself!

23. Application of the SR Latch
An important application of SR latches is for recording short lived events
e.g. pressing an alarm bell in a hospital

24. Triggering method Two types of triggering method 1) Level triggering
2) Edge triggering

26. Level triggering
Two types : 1) Positive Level triggering ) Negative Level triggering
When the flip-flop is triggered the positive or negative voltage clock pulse to change its output state i.e. set or reset is called level triggering.

27. Positive Level triggering, when clock pulse is high then o/p change its state. When o/p its low than o/p does not change its state but remains in the previous state, which was at the end of the positive clock pulse.
Negative Level triggering, when clock pulse is low then o/p change its state. When o/p its high than o/p does not change its state but remains in the previous state, which was at the end of the negative clock pulse.

28. Edge triggering
Two types : 1) Positive Edge triggering ) Negative Edge triggering
Edge triggering :- o/p of flip-flop change according to input during either of positive or negative edge of clock input.

29. Positive Edge triggering ,o/p change according to i/p during positive edge of clock pulse.
Negative Edge triggering ,o/p change according to i/p during Negative edge of clock pulse.

30. Clocked SR Flip-flop
Circuit diagram
Symbol:-

31. Truth table of Clock S-R flip- flop

32. Level triggering :
Positive level triggering ( logic 1) & Negative level triggering ( logic 0)

33. Positive Edge triggering

34. Negative Edge triggering

35. Clocked S-R f/f with Preset and clear
Circuit diagram Symbol

36. Truth-table
It is asynchronous input referred as preset and clear input.
These inputs may be applied at any instant of time between clock pulse and are not in synchronous with the clock

37. Drawback of S-R F/F
When S=R=1 & S=R=0 then o/p of Q & Q either don’t change or no change or the they are invalid due to race around condition.
This disadvantages overcome by using the D flip-flop.
Application :- SR F/F used in Electronic timer.

38. D flip-flop Circuit diagram
Symbol
Truth-table

39. Clocked D flip-flop
D FF is the simple S-R FF with inverter connected between S and R input.
This flip-flop has only one input.
Circuit diagram Symbol

40. D flip-flop
Circuit diagram Symbol

41. Truth table of Clock D-F/F

42. Edge triggering of D f/f
Positive Edge triggering of D f/f
Symbol Truth table

43. Negative Edge triggering of D f/f
Symbol Truth table

44. Dflip-flop Application: Parallel data transfer. Delay elements
In digital latch.

45. J-K Flip-flop
The uncertainty in the states of an S-R Flip-flop when S=R=1 can be eliminated by converting it into J-K lip-flop.
S= J Q, R= K Q

46. J-K Flip-flop
Circuit diagram Symbol
Truth table

47. Circuit diagram of clocked J-K F-F

48. Positive Edge triggering of J-K f/f
Symbol

49. Negative Edge triggering of J-K f/f
Symbol

50. J-K F/F with Preset & Clear
Symbol Truth table:

51. Race around condition
Occurs when J=K=1i.e the flip-flop is operated in toggling mode.
Interval T0 –T1= No change condition
Interval T1 –T2= Set condition
Interval T2 –T3= Toggle condition
Interval T3 –T4= Reset condition
Multiple toggling called as race around condition.
It must be avoided using Master Slave J-K Flip-flop.

53. Application:-
Shift Register
Counter

54. T F-F
Circuit diagram Symbol
Truth table

55. Clocked T FF
Circuit diagram Symbol

56. Positive Edge Triggering of Clocked T f-f
Symbol Truth table

57. Negative Edge Triggering of Clocked T f-f
Symbol Truth table

58. Application of T FF
Frequency division
Ripple counter

59. Master slave J-K FF

60. Operation of MSJK F-F
Its combination of clocked J-K F-F & Clocked S-R-F-F.
Where clocked J-K F-F acts as Master & Clocked S-R-F-F acts as Slave.
Master is positive level triggering i.e clock=1 & slave is negative level triggering i.e clock=1

61. Circuit diagram of master slave j-k flip-flop

62. Function of master slave j-k flip-flop

63. Excitation table
S-R Flip-flop D -Flip-flop

64. Excitation table
J-K Flip-flop T -Flip-flop

65. Conversion of J-K FF to T FF
Consider TFF as Input & JK

73. Truth table of Clock S-R flip- flop
Clock S R Qn Qn Comments
Level (0) No change states
Level (0) No change states
Level (0) No change states
Level (0) No change states
Level (1) No change states
Level (1) Reset states
Level (1) Set states
Level (1) ? ? Invalid state

75. The Clocked SR Latch
In some cases it is necessary to disable the inputs to a latch
This can be achieved by adding a control or clock input to the latch
When C = 0 R and S inputs cannot reach the latch
Holds its stored value
When C = 1 R and S inputs connected to the latch
Functions as before S R Q C

76. Clocked SR Latch R S C Qn+1 X X 0 Qn Hold 0 0 1 Qn Hold 0 1 1 1 Set
Reset
1 1 1 ? Unused R R Q Q C C S S Q Q

77. Transparency The devices that we have looked so far are transparent
That is when C = 1 the output follows the input
There will be a slight lag between them 1 C
When the clock “gate” opens, changes in input take effect at outputs – transparency. Also known as “level-triggered”. t 1 D
Analogous to:
- opening a shutter to let light through a window (except when shutter closed light does not remain at level just before it closed)
- Locks in a dam a better example t 1 Q t 1 C t 1 D t 1 Q t

78. Propagation Delay, set-up and hold (for transparent circuits)
Time taken for any change at inputs to affect outputs (change on D to change on Q).
Setup time:
Data on inputs D must be held steady for at least this time before the clock changes.
Hold time:
Data on inputs D must be held steady for at least this time after the clock changes.

79. Clocked D Latch – Timing DiagramQ
clock enables input to be “seen”
output follows input in here

80. Latches - Summary
Two cross-coupled NOR gates form an SR (set and reset) latch
A clocked SR latch has an additional input that controls when setting and resetting can take place
A D latch has a single data input
the output is held when the clock input is a zero
the input is copied to the output when the clock input is a one
The output of the clocked latches is transparent
The output of the clocked D latch can be represented by the following behaviour
D C Qn+1
X 0 Qn Hold
0 1 0 Reset
1 1 1 Set

81. Latches and Flip Flops Terms are sometimes used confusingly:
A latch is not clocked whereas a flip-flop is clocked.
A clocked latch can therefore equally be referred to as a flip flop (SR flip flop, D flip flop).
However, as we shall see, all practical flip flops are edge-triggered on the clock pulse.
Sometimes latches are included within flip flops as a sub-type.

82. Flip-flops Propagation Delay
Will the output of the following circuit ever be a 1?
The brief pulse or glitch in the output is caused by the propagation delay of the signals through the gates
Make reference back to the water flow model - propagation delay is associated with the length of time taken for the water storage container

83. Latches and Flip Flops
Clocked latches are level triggered. While the clock is high, inputs and thus outputs can change.
This is not always desirable.
A Flip Flop is edge-triggered – either by the leading or falling edge of the clock pulse.
Ideally, it responds to the inputs only at a particular instant in time.
It is not transparent.

84. D-type Latch – Timing ReviewS Q C Q 1 C
The high part represents active 1, the low part active 0. t 1 D t 1 Q t

85. Positive edge-triggered D Flip-flop TimingQ C ~Q D C Q
initially unknown

86. Master Slave D Flip-flop
A negative edge triggered flip-flop
Slave
Master D Y D Q C C Q
On the negative edge of the clock, the master captures the D input and the slave outputs it.

87. The master-slave Flip-flopD P Q P Q
When C = 1 output of master (P) follows D input and because of inverted C input output of master unable to influence output of slave
When C = 1->0 master slave output influenced by master output - note masters inputs disabled at this time (i.e. Value of D just before negative clock edge copied to Q output - a negative edge triggered device)
Because of master-slave behaviour transparency removed
***** ATTENTION, Q and Q-bar in figure wrong way around. C
No matter how long the clock pulse, both circuits cannot be active at the same time.

88. D-type Positive Edge Triggered Flip-flopQ
CLK Q’ R D
The most economical flip-flop - uses fewest gates

89. JK Flip-flop The most versatile of the flip-flopsQ
The most versatile of the flip-flops
Has two data inputs (J and K)
Do not have an undefined state like SR flip-flops
When J & K both equal 1 the output toggles on the active clock edge
Most JK flip-flops based on the edge-triggered principle
+ve edge triggered
JK flip-flop
J K C Qn+1
0 0 ­ Qn Hold
0 1 ­ 0 Reset
1 0 ­ 1 Set
1 1 ­ Qn Toggle
X X X Qn Hold
The C column indicates +ve edge triggering (usually omitted)
Talk about symbols for +ve and -ve edge-triggered flip flops
Master-slave version susceptible

90. Example JK circuit J Q A C E Ck F D B ~Q K J K C Qn+1
Assume Q = 0, ~Q = 1, K = 1
Gate B is disabled (Q = 0, F = 1)
Make J = 1 to change circuit, when Ck = 1, all inputs to A = 1, E goes to 0, makes Q = 1
Now Q and F are both 1 so ~Q = 0 and the circuit has toggled.
J K C Qn+1
0 0 ­ Qn Hold
0 1 ­ 0 Reset
1 0 ­ 1 Set
1 1 ­ Qn Toggle
X X X Qn Hold

91. Timing diagram for JK Flip-flop
Negative Edge Triggered
clock J K Q
toggle
J=K=1
hold
J=K=0
reset
J= 0 K=1
set
J= 1 K=0

92. Clock Pulse
The JK flip flop seems to solve all the problems associated with both inputs at 1.
However the clock rise/fall is of finite duration.
If the clock pulse takes long enough, the circuit can toggle.
For the JK flip flop it is assumed the pulse is quick enough for the circuit to change only once.
ideal / actual edge pulse

93. JK from D Flip-flop J D Q K
CLK C Q’

94. Summary Flip flops are circuits controlled by a clock.
Triggered on the edge of the pulse to avoid races with both inputs at 1 during the clock pulse.
Because modern ic’s have a small propagation delay races can still occur.
The master-slave configuration solves this problem by having only master or slave active at any one time.

95. What you should be able to do
Explain the difference between combinational and sequential circuits
Explain the basic operation of SR and D latches.
Explain the operation of SR and JK flip flops.
Explain the operation of master-slave flip flops.
Draw simple timing diagrams for clocked latches and edge-triggered flip flops.
Define setup and hold times for a transparent latch.

96. Opeartion Operation:- S R Qn Qn c Comments
Case NC NC no change states
Case set state
Case Reset states
Case ? ? Prohibited or invalid states