1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. (Using the Sequential Circuit Approach)
Designing a Counter
(Using the Sequential Circuit Approach)
CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff
Homework 10 due today

4. Administrative Stuff Homework 11 is out
It is due on Monday Dec 9, 4pm

5. Administrative Stuff Extra Credit Homework #2 is out
Posted on the class web page
There are 4 problems
Due no later than the last lab for this semester
Submit your design on paper and demonstrate your circuit to the lab TAs using the boards in the lab.

6. Administrative Stuff Final Project (10% of your grade)
Posted on the class web page (Labs section)
This is due next week (during your lab)

7. Example: Implement a modulo-8 counter

8. Mini Review

9. Asynchronous Counters

10. A three-bit up-counter
[ Figure 5.19 from the textbook ]

11. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
[ Figure 5.19 from the textbook ]

12. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
[ Figure 5.19 from the textbook ]

13. A three-bit up-counter
The first flip-flop changes
on the positive edge of the clock
The second flip-flop changes
on the positive edge of Q0
The third flip-flop changes
on the positive edge of Q1
[ Figure 5.19 from the textbook ]

14. A three-bit up-counterQ
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
[ Figure 5.19 from the textbook ]

15. A three-bit up-counterQ
Clock 1 2
(a) Circuit
Count 3 4 5 6 7
(b) Timing diagram
The propagation delays get longer
[ Figure 5.19 from the textbook ]

16. A three-bit down-counter
[ Figure 5.20 from the textbook ]

17. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
[ Figure 5.20 from the textbook ]

18. A three-bit down-counterQ
Clock 1 2
(a) Circuit
Count 7 6 5 4 3
(b) Timing diagram
The propagation delays get longer
[ Figure 5.20 from the textbook ]

19. Synchronous Counters

20. A four-bit synchronous up-counter
[ Figure 5.21 from the textbook ]

21. A four-bit synchronous up-counter
The propagation delay through all AND gates combined must
not exceed the clock period minus the setup time for the flip-flops
[ Figure 5.21 from the textbook ]

22. A four-bit synchronous up-counterQ
Clock 1 2
(a) Circuit
Count 3 5 9 12 14
(b) Timing diagram 4 6 8 7 10 11 13 15
[ Figure 5.21 from the textbook ]

23. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
[ Table 5.1 from the textbook ]

24. Derivation of the synchronous up-counter1 2 3 4 5 6 7
Clock cycle 8 Q
changes
T0= 1
T1 = Q0
T2 = Q0 Q1
[ Table 5.1 from the textbook ]

25. A four-bit synchronous up-counter
T1 = Q0
T2 = Q0 Q1
[ Figure 5.21 from the textbook ]

26. In general we have T0= 1 T1 = Q0 T2 = Q0 Q1 T3 = Q0 Q1 Q2 …
Tn = Q0 Q1 Q2 …Qn-1

27. Inclusion of Enable and Clear capabilityQ
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

28. Inclusion of Enable and Clear capability
This is the new thing relative to
the previous figure, plus the clear_n line T Q
Clock
Enable
Clear_n
[ Figure 5.22 from the textbook ]

29. T Flip-Flop
[ Figure 5.15a from the textbook ]

30. Positive-edge-triggered
T Flip-Flop
Positive-edge-triggered
D Flip-Flop
[ Figure 5.15a from the textbook ]

31. T Flip-Flop
2-to-1 multiplexer
[ Figure 5.15a from the textbook ]

32. 2-to-1 Multiplexer Q T D

33. What is this? Q T D +
= ?

34. T Flip-Flop T D Q 1
Clock

35. T Flip-Flop D Q Q T Q Q
Clock

36. T Flip-Flop D Q Q T Q Q
Clock

37. T Flip-Flop D Q Q T Q Q
Clock

38. These two circuits are equivalent

39. What is this? Q T D

40. What is this? Q T D
D = QT + QT

41. What is this? Q T D
D = Q + T

42. What is this? D Q T
D = Q + T

43. What is this? +
= ?

44. T Flip-Flop T D Q
Clock

45. Synchronous Counter with D Flip-Flops

46. A three-bit up-counter with T flip-flopsQ
Clock
Enable

47. A three-bit up-counter with D flip-flopsQ
Clock

48. A three-bit up-counter with D flip-flopsQ
Clock
Enable

49. A three-bit up-counter with D flip-flopsQ
Clock
Enable

50. A four-bit up-counter with T flip-flopsQ
Clock
Enable
[ Figure 5.22 from the textbook (Modified) ]

51. A four-bit up-counter with D flip-flops
[ Figure 5.23 from the textbook ]

52. End of Mini Review

53. Goal
Implement a modulo-8 counter using the sequential circuit approach
In other words, the counting sequence must be
0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, …
The count changes based on the input signal w:
If w=0, then the count remains the same
If w=1, then the count is advanced by one

54. State diagram for the counterw = 1
A/0
B/1
C/2
D/3
E/4
F/5
G/6
H/7
[ Figure 6.60 from the textbook ]

55. State table for the counter
Present
Next state
Output
state w = 1 A B C D 2 E 3 F 4 G 5 H 6 7
[ Figure 6.61 from the textbook ]

56. State-assigned table for the counter
Present
Next state
state w = 1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H
[ Figure 6.62 from the textbook ]

57. K-map for Y0 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2

58. K-map for Y0 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2

59. K-map for Y0 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 1 y wy 2

60. K-map for Y0 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 1 y wy 2 Y + =

61. K-map for Y1 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2

62. K-map for Y1 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2

63. K-map for Y1 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 1 y wy 2

64. K-map for Y1 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 1 y wy 2 Y + =

65. K-map for Y2 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2

66. K-map for Y2 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2

67. K-map for Y2 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 1 y wy 2

68. K-map for Y2 Present Next state state w = 1 Count y Y z A 000 001 B1
Count y 2 Y z A
000
001 B
010 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 1 y wy 2

69. Karnaugh maps for D flip-flops for the counter00 01 11 10 1 y wy 2 Y + = 00 01 11 10 1 y wy 2 Y + = 00 01 11 10 1 y wy 2 Y = wy + y y + y y + w y y y 2 2 2 1 2 1 2
[ Figure 6.63 from the textbook ]

70. Circuit diagram for the counter implemented with D flip-flops
[ Figure 6.64 from the textbook ]

71. Circuit diagram for the counter What is this? implemented
with D flip-flops
What is this?
[ Figure 6.64 from the textbook ]

72. Circuit diagram for the counter XOR implemented with D flip-flops
[ Figure 6.64 from the textbook ]

73. We can simplify all three expressions

74. We can simplify all three expressions

75. A three-bit counter with D flip-flopsQ
Clock
Enable

76. A four-bit counter with D flip-flops
[ Figure 5.23 from the textbook ]

77. Summary
The up-counters that we studied in Chapter 5 can now be derived using the sequential circuit approach
We get the same circuit diagrams as before

78. Example 2: Implement a modulo-8 counter using JK Flip-Flops

79. JK Flip-Flop
D = JQ + KQ
[ Figure 5.16a from the textbook ]

80. JK Flip-Flop ( ) (b) Truth table (c) Graphical symbol (a) Circuit J Q1 t + ( )
(b) Truth table
(c) Graphical symbol D
Clock
(a) Circuit
[ Figure 5.16 from the textbook ]

81. JK Flip-Flop (How it Works)
A versatile circuit that can be used both as a SR flip-flop and as a T flip flop
If J=0 and S =0 it stays in the same state
Just like SR It can be set and reset
J=S and K=R
If J=K=1 then it behaves as a T flip-flop

82. Rules for J and K inputs Current State Next State of the Flip-flop
From 0 to 0 J=0 and K= d
From 0 to 1 J=1 and K= d
From 1 to 0 J=d and K= 1
From 1 to 1 J=d and K= 0

83. Excitation table for the counter with JK flip-flops
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H
[ Figure 6.65 from the textbook ]

84. Karnaugh maps for the first JK flip-flop
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2

85. Karnaugh maps for the first JK flip-flop
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2 J0 K0

86. Karnaugh maps for the first JK flip-flop
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 y 1 wy 2 J0 K0

87. Karnaugh maps for the first JK flip-flop
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 d 1 y wy 2 J0 K0

88. Karnaugh maps for the first JK flip-flop
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 d 1 y wy 2 J0 K0

89. Karnaugh maps for the first JK flip-flop
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 d 1 y wy 2 J0 K0

90. Karnaugh maps for the first JK flip-flop
Present
Flip-flop inputs
state w = 1
Count y 2 Y J K z A
000 0d
001 1d B d0
010 d1 C
011 D
100 E
101 F
110 G
111 H 00 01 11 10 d 1 y wy 2 J w = K J0 K0

91. Karnaugh maps for the first JK flip-flop00 01 11 10 d 1 y wy 2 J w = K J0 K0
[ Figure 6.66 from the textbook ]

92. Karnaugh maps for the second JK flip-flop00 01 11 10 d 1 y wy 2 J = K J1 K1
[ Figure 6.66 from the textbook ]

93. Karnaugh maps for the third JK flip-flop00 01 11 10 d 1 y wy 2 J = K J2 K2
[ Figure 6.66 from the textbook ]

94. Circuit diagram using JK flip-flops

95. Circuit diagram using JK flip-flops
[ Figure 6.67 from the textbook ]

96. Factored-form implementation of the counter
[ Figure 6.68 from the textbook ]

97. Another Example (A Different “Counter”)

98. Goal
Implement a 3-bit counter using the sequential circuit approach that counts the pulses on the input line w.
The counter must count in the following sequence:
0, 4, 2, 6, 1, 5, 3, 7, 0, 4, 2, …
The count must be represented directly by the flip-flop values. No extra gates are allowed.
In other words, count = Q2 Q1 Q0
The count changes based on the input signal w:
If w=0, then the count remains the same
If w=1, then the count is advanced by one

99. Goal
Implement a 3-bit counter using the sequential circuit approach that counts the pulses on the input line w.
The counter must count in the following sequence:
0, 4, 2, 6, 1, 5, 3, 7, 0, 4, 2, …
The count must be represented directly by the flip-flop values. No extra gates are allowed.
In other words, count = Q2 Q1 Q0
The count changes based on the input signal w:
If w=0, then the count remains the same
If w=1, then the count is advanced by one
Clock = w

100. By flipping the order of the bits we get
000
001
010
011
100
101
110
111
000
100
010
110
001
101
011
111

101. By flipping the order of the bits we get1 2 3 4 5 6 7
000
001
010
011
100
101
110
111
000
100
010
110
001
101
011
111 4 2 6 1 5 3 7

102. State table for the counterlike example
Present
Next
Output
state z 2 1 A B
000 C
100 D
010 E
110 F
001 G
101 H
011
111
[ Figure 6.69 from the textbook ]

103. State-assigned table for this example
Present
Next
Output
state
state y y y Y Y Y z z z 2 1 2 1 2 1
000 1 00 00
100 10 1 00
010 1 10 10
110 01 1 10
001 1 01 01
101 11 1 01
011 1 11 11
111 00 1 11
[ Figure 6.70 from the textbook ]

104. K-maps for Y2, Y1, and Y0 Present Next Output state y Y z 000 00 100Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

105. K-maps for Y2, Y1, and Y0 Notice that these are scrambled Present Next
Output
state y 2 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10
Notice that these
are scrambled

106. K-maps for Y2, Y1, and Y0 Notice that these are scrambled Present Next
Output
state y 2 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10
Notice that these
are scrambled

107. K-map for Y2 Present Next Output state y Y z 000 00 100 10 010 110 01Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

108. K-map for Y2 Present Next Output state y Y z 000 00 100 10 010 110 01Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

109. K-map for Y2 Present Next Output state y Y z 000 00 100 10 010 110 01Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

110. K-map for Y2 Y2= y2 Present Next Output state y Y z 000 00 100 10 010Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10
Y2= y2

111. K-map for Y1 Present Next Output state y Y z 000 00 100 10 010 110 012 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

112. K-map for Y1 Present Next Output state y Y z 000 00 100 10 010 110 012 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

113. K-map for Y1 Present Next Output state y Y z 000 00 100 10 010 110 012 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

114. K-map for Y1 Y1= y2y1 + y2 y1 XOR Present Next Output state y Y z 000Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10
Y1= y2y1 + y2 y1
XOR

115. K-map for Y0 Present Next Output state y Y z 000 00 100 10 010 110 012 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10

116. K-map for Y0 Present Next Output state y Y z 000 00 100 10 010 110 012 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10 1

117. K-map for Y0 Y0= y1y0 + y2 y0 + y2 y1 y0 Present Next Output state y YY z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10 1
Y0= y1y0 + y2 y0 + y2 y1 y0

118. K-map for Y0 Y0= y1y0 + y2 y0 + y2 y1 y0 = ( y1 + y2 ) y0 + y2 y1 y0
Present
Next
Output
state y 2 1 Y z
000 00
100 10
010
110 01
001
101 11
011
111 y 1 2 00 01 11 10 1
Y0= y1y0 + y2 y0 + y2 y1 y0
= ( y1 + y2 ) y0 + y2 y1 y0
= ( y1 y2 ) y0 + (y2 y1) y0
= ( y1 y2 ) + y0

119. Let’s Draw the Circuit for this exampleQ z 1 2 w

120. Let’s Draw the Circuit for this exampleQ z 1 2 w
Y2= y2
Y1 = y1 + y2
Y0 = ( y1 y2 ) + y0

121. The Circuit for this exampleD Q z 1 2 w
Y2= y2
Y1 = y1 + y2
Y0 = ( y1 y2 ) + y0
[ Figure 6.71 from the textbook ]

122. Questions?

123. THE END