1. Design For Testability
강 성 호 (연세대학교, 전기전자공학과)
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2. 과목 개요(Learning Map)
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3. 목 차 Introduction Testability Scan BIST JTAG Summary Logic BIST
Memory BIST
JTAG
Summary
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4. Potential Yield Losses
While tester accuracy has improved at a rate of 12% per year, semiconductor speeds have improved at 30% per year
If current trends continue, in less than ten years, tester timing errors will approach the cycle time of the fastest devices
Year of First Produce Shipment
1997
1999
2001
2003
2006
2010
2012
Yield (%)
Device period (ns)
1.3
1.1
0.91
0.77
0.59
0.43
0.33
Test accuracy (ns)
0.2
0.19
0.18
0.175
Solutions Exist
Solutions Being Pursued
No Known Solution
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5. Why Test? Why Add Test Logic?
Measurement of defects & quality level
Incoming inspection contractual
Perceived product quality by customer
Reliability requirement contractual
Why add test logic?
To increase the test coverage
To reduce the time it takes to quality the part
To reduce the cost-of-test
Design For Testability
The act of adding logic or features to enhance the testability of a design is generally referred to as Design-for-Test (DFT)
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6. External ATE Cost
High End ATE cost per pin is essentially flat for the past 20 years at around $10K/pin
Total ATE purchases annually is essentially flat at around 3% to 5% of the semiconductor revenues
It takes another 3X to 4X in test engineering, equipment maintenance and more to determine complete cost of testing
By 2012, it may cost more to test a transistor than to manufacture the transistor
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7. Design for Testability (DFT)
Benefit of DFT
Having the ability to measure the quality level deterministically
Making it easier to generate the necessary vectors
Making it possible to support all test environments easily
Wafer probe / Engineering debug / Manufacturing test
Yield enhancement and failure analysis
Allowing the cost-of-test to reduced in all environments
Reduces tester complexity (and cost)
Reduces test time (and cost)
Reduces tester requirements (pins, memory depth, pin timing)
Cost of DFT
Adds complexity to design methodology
Impacts design power & package pins
Impacts design speed or performance
Adds to silicon area
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8. Full Timing Simulation
DFT Flow
DFT Rule Checking
Scan Design, Boundary Scan Design
Memory BIST Design, Logic BIST Design
Static Timing Analysis
Test Pattern Generation
Logic Simulation
Test Vector Translation
Full Timing Simulation
Test Synthesis
Verilog/VHDL Netlist
ATPG
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9. Contents Testability Introduction Scan BIST JTAG Summary Logic BIST
Memory BIST
JTAG
Summary
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10. Testability Measures Testability
Inherent property of the circuit based on the circuit topology
Probability that a fault is detected by a random vector
Function of controllability and observability
Controllability
Ability to establish a specific signal value at each node in the circuit by setting values on the circuit inputs
Observability
Ability to determine the signal value at any node in a circuit by controlling primary inputs and observing its outputs
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11. SCOAP Compute relative complexity to control and observe
6 Numbers for Each Node, N
CC0, CC1, C0, SC0, SC1, S0
Combinational Measure
Roughly proportional to #circuit lines that must be set to control or observe given line
Sequential Node
Roughly proportional to #times a flip-flop must be clocked to control or observe given line
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12. SCOAP
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13. Example
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14. Design for Testability
Difficulty in ATPG
Not effective for large sequential circuits
Advantages
Test generation is easy
High quality testing
Disadvantages
Area overhead
Timing overhead
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15. Classification of DFT Ad-Hoc Design Structured Design Initialization
Adding extra test points
Circuit partitioning
Structured Design
Scan design
Scan Path
Level Sensitive Scan Design
Random Access Scan
Boundary Scan
Built-in Self Test
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16. Ad Hoc Techniques
Techniques which can be applied to a given product, but are not directed at solving the general problem
Cost is lower than that of structured approaches (Scan, BIST, etc.)
The job of doing test generation and fault simulation are usually not as simple or as straightforward
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17. Ad Hoc Techniques Test points
Employ test points to enhance controllability and observability
Large demand on extra I/O pins
Example
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18. Ad Hoc Techniques Partitioning
Partition large circuits into smaller subcircuits to reduce test generation cost
Example
T1=0 T2=0 : Normal Mode
T1=0 T2=1 : Test C1
T1=1 T2=0 : Test C2
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19. Ad Hoc Techniques Initialization
Process bringing a sequential circuit into a known state at some known time
Circuits requiring some clever initialization sequence should be avoided
Design circuits to be easily initializable
Flip-flop with explicit clear
Use explicit clear to all FFs
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20. Ad Hoc Techniques Avoid gated clock
Make sure EN settles before CLK changes
Or redesign the circuit as follows
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21. Contents Scan Introduction Testability BIST JTAG Summary Logic BIST
Memory BIST
JTAG
Summary
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22. Scan
Scan is a test methodology that allows one to control and observe all internal nodes in a synchronous design
Application for finite state machines
Combinational and sequential elements tested separately
Logic Test
Two mode operation
Normal mode
Test mode
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23. Advantages of Scan Design
Structured design is possible
Can use combinational ATPG
Significant reduction of test generation time
High fault coverage
Ease of fault diagnosis
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24. Disadvantages of Scan Design
Additional circuitry is added to FF
SCAN flip-flop is more expensive
Additional chip area
Additional circuit pins
Test time increase
Due to shift in and shift out
Some designs are not easily realizable as scan designs
Need to store Patterns
Motivation for BIST
Inability to test circuits at full speed
Motivation for Delay Fault Testing
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25. Full Scan All flip-flops of the circuit have the scan capability
All flip-flops are substituted with scan cells
<Synchronized Sequential Logic>
scan insertion
<Circuit applied full scan>
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26. Scan Cells Muxed scan Clocked scan LSSD Easy control Hardware overhead
Performance overhead
Clocked scan
Control overhead
Lower hardware overhead
Better performance
LSSD
Level Sensitive Scan Design
Design rules imposed on designers
Slow test application
normal-speed testing is impossible
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27. Scan Test Vectors
Sequence length = (Ncomb + 1) Nsff + Ncomb clock periods
Ncomb = number of combinational vectors
Nsff = number of scan flip-flops
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28. Scan Test Sequences Scan load/unload Scan data apply Scan sample
This action will serially shift data into the chip from scan element to scan element
Scan data apply
Scan chain is applying a predetermined calculated data state directly to the internal logic
Scan sample
Data including any fault effect is captured into scan flip-flop
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29. Partial Scan Full scan is not always feasible
Retains many advantages of full scan and reduces the cost
Exclude certain flip-flops
Fault coverage is a function of the number of scan FFs
Main researches
Flip-flop selection
Test length reduction
Retiming
What do we lose in partial scan?
Loss of fault coverage
Difficult to automate in synthesis environments
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30. Partial Scan How to choose scan FFs and non-scan FFs?
Testability Analysis
Structural Analysis
ATPG Based Analysis
Used in conjunction with other schemes
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31. General Scan Design Rules
Disable asynchronous clears and presets during scan (Required)
Most scan types require all asynchronous clears and presets for scan registers to be inactive in the scan mode, so that bits in the scan chain are not cleared as the scan chain is loaded
Eliminate internal tristate contention during scan (Required)
If internal busses do exist in the design, during scan mode the circuit can be put into a random state that may cause internal bus contention
Prevent multiple drivers
Disable all drivers with the scan enable signal
Add decoding logic to ensure that only one tristate enable is turned on at any time
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32. General Scan Design Rules
Disable write signals for RAMs during scan (Required)
Important to preserve the content of the RAMs, as well as FIFOs and register files
Disable W EN to the RAM with the SCAN EN
Disable bidirectional output buffer during scan (Strongly Recommended)
During the scan mode, registers along the scan chain will be toggled frequently, thus turning on and off the bidirectional buffers, causing undesirable current spikes
Avoid cross coupled NANDs or NORs (Strongly Recommended)
Timing simulation(Strongly Recommended)
The shifting of data through the scan chain should be thoroughly simulated to verify that there are no timing violations or internal bus contentions due to the scan operation
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33. General Scan Design Rules
No combinational Feedback Loops (Strongly Recommended)
Use multiple scan chains (Recommended)
Test time is related to the length of scan chain
The scan enable pin can be shared
Multiple chains of different lengths are allowed
Scan chain loading using (Recommended)
When fanout problem in Q
Use lock-up latches (Recommended)
Lock-up latches may be necessary between the scan out and scan in of major blocks or when scan chains switches to a separate clock driver to avoid side effects of clock skew
Make RAMs reasonably controllable (Recommended)
Fully synchronous Design (Recommended)
No gated or internally generated clocks
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34. Contents BIST Logic BIST Introduction Testability Scan JTAG Summary
Memory BIST
JTAG
Summary
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35. Built In Self Test Test patterns are generated on-chip
Responses to the test patterns are evaluated on chip
External operations are required only to initialized the built-in tests and to check the test results (go/no-go)
Test/
Normal
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36. Built In Self Test Advantage Disadvantages
No need for expensive tester
At-speed testing
Thorough test
Disadvantages
Initial Design Investment
Area overhead
Pin overhead
Not effective for random testing resistive circuits
Aliasing problem
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37. General BIST Architecture (Test-per-Scan)
Advantages
BIST control is simple
Hardware overhead is small
Low impact on system performance
Disadvantages
Serial pattern generation causes long test times
The function of the CUT may not be tested at speed
Circuit
Under
Test
Scan chain
Pattern
Generator
Response
Analyzer
Test-per-scan
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38. General BIST Architecture (Test-per-Clock)
Advantages
Short test times
High speed test can be implemented
Disadvantages
BIST controller is complex
Integrating test registers into the data path has a impact on system performance
In general, Test Pattern Generator & Response Analyzer are implemented using LFSR & MISR in both test-per-scan and test-per-clock BIST
Circuit
Under
Test
Test Pattern
Generator
Response
Analyzer
Test-per-clock
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39. Test Pattern Generation
Stored pattern
Store deterministic test patterns in a ROM
Too expensive
Exhaustive pattern
Apply all possible 2n patterns to a circuit with n inputs
Pseudo exhaustive pattern
Break circuit into small, overlapping blocks and test each exhaustively
Pseudo random pattern
Algorithmic pattern generator that produces a subset of all possible tests with most of the properties of randomly-generated patterns
Preferred method
Usually implemented with LFSR
Weighted random pattern
Deterministic pattern
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40. Pseudo Random Pattern Generation
LFSR (Linear Feedback Shift Register)
Simple and Regular Structure
Compatible with scan DFT design
Capable of exhaustive and/or pseudo exhaustive testing
Low aliasing probability D1 D2 D3 D4 +
Type 1
Type 2
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41. Pseudo Random Pattern Generation
Examples
Characteristic Polynomial : 1+x2+x3
Initial condition (1,0,0) : x
Q1 : x / (1+x2+x3)
Q2 : x2 / (1+x2+x3)
Q3 : x3 / (1+x2+x3)
When initial state is 100
Q1 Q2 Q3
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42. Deterministic Test Pattern Generation
Problem with pseudo random test
Very long test application time
Low fault coverage : Random Pattern Resistant Fault
Deterministic BIST
Combining pseudorandom test with deterministic test
Store and generation
Bit-fixing
Bit-flipping
Multiple-polynomial LFSR id
seed . .
CUT
Polynomial
selection
Output data
evaluation
LFSR
Scan chain
feedback
<Deterministic BIST using Multiple-polynomial LFSR>
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43. Response Analyzer Compression
Bit-to-bit comparison is infeasible for BIST
The response analyzer compresses a very long test responses into a single word. Such a word in called a signature
The signature is then compared with the prestored golden signature obtained from the fault-free responses
Many output sequences may have the same signature after the compression, the aliasing problem
Compression
Signature : output of the compactor
Decision factors
Extra hardware
Loss of fault coverage
Calculation of good signature
Aliasing
A faulty circuit produces a signature that is identical to the signature of a fault free circuit
Ones count, transition count, parity check, syndrome
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44. Response Analyzer MISR (Multiple Input Shift Register)
Normally, a single input signature analyzer is not used due to testing overhead
Aliasing Probability : 1/2n
All error patterns are equally likely
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45. STUMPS Self Testing Using MISR and Parallel SRSG
Centralized and separate BIST
Multiple scan paths
Reduction in test time
No boundary scan
Lower overhead than BILBO but takes longer to apply
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46. BILBO(Built-In Logic Block Observer)
B1 B Mode
Normal Mode
Reset
Shift Register
Signature Analyzer
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47. Contents BIST Memory BIST Introduction Testability Scan Logic BIST
JTAG
Summary
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48. Concurrent Memory BIST
A concurrent memory BIST is performed during normal use of the chip
Faults occurring during normal use can be detected
Hardware overhead is large because it requires logic circuitry for generating the redundant information to write, read and store
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49. Non-concurrent Memory BIST
A non-concurrent memory BIST is performed only in test mode
Most BIST implementations are non-concurrent
The test does not have to preserve the data which is stored on the chip
Faults which are not covered by the fault models and faults occurring between BIST periods will obviously not be detected
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50. Transparent BIST
A non-concurrent memory BIST is said to be transparent if at the end of the test session, the contents of the RAM are equal to its initial contents
Transparent memory BIST are very suitable for periodic testing because they ensure that normal operation on the memory data can be continued between periodic test sessions
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51. Traditional Memory BIST Architecture
BIST architecture based on March test algorithm
Address generator
log2n bits counter
Wait counter
Measurement of wait time to test DRF
Address counter
Data generator
Data generation for memory testing
Data comparator
Comparison and storage of data from memory
BIST controller
Control circuitry for BIST circuit
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52. Built In Self Repair of Memory
BIST can only identify faulty chip
Laser cut may be infeasible in some cases
Two types
Using Fault-array comparator
Repair by cell
Repair by column
Using switch array
<BISR using switch array>
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53. Contents JTAG Introduction Testability Scan BIST Logic BIST
Memory BIST
JTAG
Summary
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54. Boundary Scan Improve testability Purpose of using Boundary Scan
JTAG (Joint Test Action Group) Boundary Scan Standards
IEEE P1149.1
Purpose of using Boundary Scan
Testing interconnections among chips
Testing each chip
Snapshot observation of normal system data
Board Test Philosophy
As a sorting process
As a repair driver
As a process monitor
Used for
Chips, chip interconnections, modules, module interconnections, subsystems, multi-chip modules
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55. Concept of Boundary Scan Test
Board containing 4 chips with one serial test path
serial shift
parallel output
parallel capture serial shift
Detect and diagnose of logical faults at the board level
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56. Basic Chip Architecture of 1149.1
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57. Hardware Components of 1149.1
TAP
Test Access Port
TMS, TCK, TDI, TDO, TRST* (optional)
TAP Controller
Finite state machine with 16 states
Input : TCK, TMS
Output : 9 or 10 signals including ClockDR, UpdateDR, ShiftDR, ClockIR, UpdateIR, ShiftIR, Select, Enable, TCK, and the optional TRST* IR
Instruction Register
TDR
Test Data Register
Mandatory : boundary scan register and bypass register
Optional : devie-ID register, design-specific registers, etc.
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58. Boundary Scan Cells Normal Mode Scan Mode Capture Mode Update Mode
When Mode = 0, data passes from In to Out
Then the cell is transparent to the application logic
Scan Mode
ShiftDR = 1 and clock pulses are applied to ClockDR
Capture Mode
The data on In can be loaded into the scan path by setting ShiftDR = 0 and applying one clock pulse to ClockDR
Update Mode
Once the 1st FF is loaded, either by a capture or scan operation, its value can be applied to Out by setting Mode = 1 and applying clock pulse to UpdateDR
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59. TAP Controller State Diagram
State transitions occur on rising edge of TCK based on the current state and the TMS input value only
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60. Selected Data Register
Instruction Summary
Instruction
Opcode
Mode
Selected Data Register
Remarks
EXTEST
All zero
Test
Boundary
Mandatory
SAMPLE/
PRELOAD
User-specified
Normal
BYPASS
All one
Bypass
INTEST
Optional
RUNBIST
IDCODE
Device-ID
USERCODE
CLAMP
HIGHZ
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61. EXTEST
Test Interconnection between chips and board
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62. INTEST
Test the on-chip system logic
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63. SAMPLE
Get snapshot of normal chip output signals
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64. PRELOAD
Load data into test data update register
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65. Interconnect Test
Interconnect test refers to the testing for shorts and opens within the nodal wiring between Boundary-Scan components only
Interconnect test is performed using EXTEST instruction
Fault model
Short fault
AND short
OR short
Strong driver short
Stuck-at fault
Stuck-at 1
Stuck-at 0
Stuck open
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66. Interconnect Test
We diagnose failure by examining the SRVs that are incorrect and by trying to decide what could have caused the discrepancies
Aliasing and confounding do not harm the ability of interconnect testing to detect shorts, but complicate the diagnosis of faults
Aliasing
Aliasing occurs when the combined failures of two or more modes results in an SRV matching the STV of yet another node
Confounding
A confounding test result may occur when the test results from the multiple, independent faults are identical
OR short
<Aliasing>
OR type
<Confounding>
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67. Interconnect Test Sequences
Modified Counting sequence
Test length : log2(N+2)
Short and stuck-at fault
Aliasing and confounding problem
True/complement counting sequence
Test length : 2[log2(N+2)]
Aliasing free
Confounding problem
Walking one sequence
Test length : N
Aliasing and confounding free
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68. Interconnect Test Using 1149.1
PTV
Short (wired-AND)
serial shift out
STV
101
001
011
001
001
001
110
000
Stuck-open (stuck-at-0)
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69. SoC and Test-Wrapper Test wrapper
Surrounds a (hard) core with test logic
Provides various modes of operation
Normal mode
External test mode
Internal test mode
Bypass mode
Isolation mode
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70. SoC and Test Access Mechanism
Deliver test stimuli from the test source to the CUT and transport test responses from the CUT to the test sink
TAM design considerations
Data transport capacity (TAM width)
Test time
TAM overhead
TAM design architecture
Multiplexing architecture
Daisy chain architecture
Distributed architecture
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71. Contents Summary Introduction Testability Scan BIST Logic BIST
Memory BIST
JTAG
Summary
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72. Summary
Solving the test problem is critical to producing the next generation of integrated circuits
For efficient SOC test, not only DFT at the core design but also DFT at the core integration must be considered
Testability is another design requirement like area, speed and power
Design, testing and manufacturing should become more closely interrelated
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73. References
M. Abramovich, M. A. Breuer, and A. D. Friendman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.
M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-signal VLSI Circuits, Kluwer Academic Publishers, Boston, 2000.
V. D. Agrawal and M. R. Mercer, “Testability Measures-What Do They Tell Us?,” Digest of Papers 1982 Intn’l. Test Conf., pp , November, 1982.
S. J. Chandra and J. H. Patel, “Experimental Evaluation of Testability Measures for Test Generation,” IEEE Trans. on Computer-Aided Design, Vol. CAD-8, No. 1, pp.93-97, January, 1989.
P. G. Kovijanic, “Computer Aided Testability Analysis,” Proc. IEEE Automatic Test Conf., PP , 1979.
E. B. Eichelberger and T. W. Williams, “ A Logic Design Structure for LSI Testing,” Proc. 14th Design Automation & Fault-Tolerant Computing, Vol. 2, No. 2, pp , May, 1978.
J. Grason and A. W. Nagel, “Digital Test Generation and Design for Testability,” Journal Digital Systems, Vol. 5, No. 4, pp , 1981.
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74. References
D. T. Tang and C. L. Chen, “Logic Test Pattern Generation Using Linear Codes,” IEEE Trans. on Computers, Vol. C-32, No. 12, pp , 1983.
P. H. Bardell, W. H. Maanney, and J. Savir, Built-In Test for VLSI Pseudorandom Techniques, A Wiley-Interscience Publication, New York, 1987.
A. J. Van de Goor, Testing Semiconductor Memories, John Wiley & Sons, New York, 1991.
P. Mazumder, Testing and Testable Design of High-Density Random-Access Memories, Kluwer Academic Publishers, Boston, 1996.
K. P. Parker, The Boundary-Scan Handbook, Kluwer Academic Publishers, Boston, 2003.
P. T. Wagner, “Interconnect Testing with Boundary-Scan,” Proc. Intn’l. Test Conf., pp , September, 1987.
L. Whetsel, “A View of the JTAG Port and Architecture,” ATE Instrumentation Conf. West, pp , January, 1988.
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