1. Test Fixture (Testbench)
Much more like programming! =:0
Generate clock and reset
Apply stimulus
Check results (optional)
Terminate simulation (recommended)
Add test fixture as a “simulation source” under “Add Sources”

2. // Instantiate the Unit Under Test (UUT) top uut ( .clk(clk),
`timescale 1ns / 1ps
module tb;
// Inputs
logic clk;
logic rst;
logic load;
logic [7:0] din;
// Outputs
logic [7:0] gcd_rslt;
logic done;
// Instantiate the Unit Under Test (UUT)
top uut (
.clk(clk),
.rst(rst),
.load(load),
.din(din),
.gcd_rslt(gcd_rslt),
.done(done) );
[...]
Note: The tb module has no inputs or outputs on its interface
Only a single component instantiation
Internal signals correspond to UUT interface
reg type indicates signals that will be generated internally by the testbench via procedural assigns
time scale means the unit multiplier for delays is ns with a resolution of 1 ps, so you could delay
1.001 ns.

3. Clock Generation [...] parameter CLK_PRD = 100; // 10 MHz clock
parameter HOLD_TIME = (CLK_PRD*0.3);
initial begin
clk <= 0;
forever #(CLK_PRD/2) clk = ~clk;
end
Define the clock period and hold time requirements.
The “initial” keyword identifies a single-pass behavior that will only “execute” once.
In this case it generates a periodic waveform.
Forever loop with a single statement
The “#” is a delay construct that allows simulation time to advance before execution continues
Basically, after specified delay (in nsec), exectute the statement.
Note the mix of blocking and non-blocking. Not recommended for synthesis, only testbenches
Initial assignment with non-blocking is to allow other initial blocks to evaluate at start-up (I think!)

4. Reset and Stimulus Alignment
initial begin
// Initialize Inputs
rst = 0;
load = 0;
din = 8'bx;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
@(posedge clk); // align with clock edge
#HOLD_TIME; // offset a hold time
repeat(2) #CLK_PRD; // Now only wait integer clock periods
rst = 1; #CLK_PRD;
repeat(2) #CLK_PRD; [...]
FPGA include a global set/reset after configuration that is modeled in post-implementation simulation, so you want your testbench to wait.
@ is an event control operator with a sensitivity list
Followed by #hold sets stimulus at a hold time after rising edge. din set to all “x”
clock twice to allow X to propagate, then reset for 1 cc, then clock two more cycles to make sure it stays initialized

5. Stimulus and Done Check
[...] load = 1; #CLK_PRD;
load = 0; din = 8'd27; #CLK_PRD;
din = 8'd18; #CLK_PRD;
din = 8'bx; #CLK_PRD;
begin : run_loop
forever
begin
@(posedge clk);
if (done) disable run_loop;
end
end // run_loop
$finish;
endmodule
din set back to “x”
Named forever loop to allow break on done
$finish is a system task that returns control to the simulator
Will run forever if done never asserted, causing simulator to appear to lock up
Better is to include a max sim constraint using a single cycle block

6. Simulation Termination
parameter MAX_SIM_TIME = (100*CLK_PRD);
initial #(MAX_SIM_TIME) $finish;
Allows a maximum simulation time of 100 clock cycles