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Memory Systems CH008.

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Presentation on theme: "Memory Systems CH008."— Presentation transcript:

1 Memory Systems CH008

2 Figure 8.1 The memory interface
Copyright © 2016 Elsevier Ltd. All rights reserved.

3 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.2 Diverging processor and memory performance. Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2011. Copyright © 2016 Elsevier Ltd. All rights reserved.

4 Figure 8.3 A typical memory hierarchy
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5 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.4 Memory hierarchy components, with typical characteristics in 2015 Copyright © 2016 Elsevier Ltd. All rights reserved.

6 Figure 8.5 Mapping of main memory to a direct mapped cache
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7 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.6 Cache fields for address 0xFFFFFFE4 when mapping to the cache in Figure 8.5 Copyright © 2016 Elsevier Ltd. All rights reserved.

8 Figure 8.7 Direct mapped cache with 8 sets
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9 Figure 8.8 Direct mapped cache contents
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10 Figure 8.9 Two-way set associative cache
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11 Figure 8.10 Two-way set associative cache contents
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12 Figure 8.11 Eight-block fully associative cache
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13 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.12 Direct mapped cache with two sets and a four-word block size Copyright © 2016 Elsevier Ltd. All rights reserved.

14 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.13 Cache fields for address 0x C when mapping to the cache of Figure 8.12 Copyright © 2016 Elsevier Ltd. All rights reserved.

15 Figure 8.14 Cache contents with a block size b of four words
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16 Figure 8.15 Two-way associative cache with LRU replacement
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17 Figure 8.16 Memory hierarchy with two levels of cache
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18 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.17 Miss rate versus cache size and associativity on SPEC2000 benchmark. (Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2012.) Copyright © 2016 Elsevier Ltd. All rights reserved.

19 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.18 Miss rate versus block size and cache size on SPEC92 benchmark. (Adapted with permission from Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th ed., Morgan Kaufmann, 2012.) Copyright © 2016 Elsevier Ltd. All rights reserved.

20 Copyright © 2016 Elsevier Ltd. All rights reserved.
Figure 8.19 Hard disk Copyright © 2016 Elsevier Ltd. All rights reserved.

21 Figure 8.20 Virtual and physical pages
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22 Figure 8.21 Physical and virtual pages
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23 Figure 8.22 Translation from virtual address to physical address
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24 Figure 8.23 The page table for Figure 8.21
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25 Figure 8.24 Address translation using the page table
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26 Figure 8.25 Address translation using a two-entry TLB
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27 Figure 8.26 Hierarchical page tables
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28 Figure 8.27 Address translation using a two-level page table
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29 Figure 8.28 Building blocks
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30 Figure 8.29 Computer system
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31 Copyright © 2016 Elsevier Ltd. All rights reserved.

32 Copyright © 2016 Elsevier Ltd. All rights reserved.

33 Copyright © 2016 Elsevier Ltd. All rights reserved.
Fig u08-01 Copyright © 2016 Elsevier Ltd. All rights reserved.

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